JAJSCF1A August   2016  – November 2017 LM5161-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Circuit
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Soft-Start
      5. 7.3.5  Error Transconductance (GM) Amplifier
      6. 7.3.6  On-Time Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  N-Channel Buck Switch and Driver
      9. 7.3.9  Synchronous Rectifier
      10. 7.3.10 Enable / Undervoltage Lockout (EN/UVLO)
      11. 7.3.11 Thermal Protection
      12. 7.3.12 Ripple Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Pulse Width Modulation (FPWM) Mode
      2. 7.4.2 Undervoltage Detector
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM5161-Q1 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Resistor Divider Selection
          3. 8.2.1.2.3  Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  Series Ripple Resistor - RESR (FPWM = 1)
          7. 8.2.1.2.7  VCC and Bootstrap Capacitor
          8. 8.2.1.2.8  Input Capacitor Selection
          9. 8.2.1.2.9  Soft-Start Capacitor Selection
          10. 8.2.1.2.10 EN/UVLO Resistor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LM5161-Q1 Isolated Fly-Buck (36-V to 72-V Input, 12-V, 12-W Isolated Output)
        1. 8.2.2.1 LM5161-Q1 Fly-Buck Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Selection of VOUT and Turns Ratio
          2. 8.2.2.2.2 Secondary Rectifier Diode
          3. 8.2.2.2.3 External Ripple Circuit
          4. 8.2.2.2.4 Output Capacitor (CVISO)
        3. 8.2.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 関連資料
    3. 11.3 商標
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
Input voltage VIN to AGND –0.3 100 V
EN/UVLO to AGND –0.3 100
RON to AGND –0.3 100
BST to AGND –0.3 114
VCC to AGND –0.3 14
FPWM to AGND –0.3 14
SS to AGND –0.3 7
FB to AGND –0.3 7
Output voltage BST to SW –0.3 14 V
BST to VCC 100
SW to AGND –1.5 100
SW to AGND (20-ns transient) –3
Maximum junction temperature (3) –40 150 °C
Storage temperature Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions(1)

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN input voltage 4.5 100 V
IO output current 1 A
External VCC bias voltage 9 13 V
Operating junction temperature(2) –40 150 °C
(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.4 Thermal Information(1)

THERMAL METRIC LM5161-Q1 UNIT
PWP (HTSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance(1) 39.3 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance(1) 2.0 °C/W
ψJB Junction-to-board thermal characteristic parameter 19.3 °C/W
RθJB Junction-to-board thermal resistance 19.6 °C/W
RθJCtop Junction-to-case (top) thermal resistance 22.8 °C/W
ψJT Junction-to-top thermal characteristic parameter 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C(1)(2) for LM5161-Q1. Unless otherwise stated, VIN = 48 V.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISD Input shutdown current VIN = 48 V, EN/UVLO = 0 V 50 90 µA
IOP Input operating current VIN = 48 V, FB = 3 V, Non-switching 2.3 2.8 mA
VCC SUPPLY
VCC Bias regulator output VIN = 48 V, ICC = 20 mA 6.3 7.3 8.5 V
VCC Bias regulator current limit VIN = 48 V 30 mA
VCC(UV) VCC undervoltage threshold VCC rising 3.98 4.1 V
VCC(HYS) VCC undervoltage hysteresis VCC falling 185 mV
VCC(LDO) VIN - VCC dropout voltage VIN = 4.5 V, ICC = 20 mA 200 340 mV
HIGH-SIDE FET
RDS(ON) High-side on resistance V(BST - SW) = 7 V, ISW = 0.5A 0.58 Ω
BST(UV) Bootstrap gate drive UV V(BST - SW) rising 2.93 3.6 V
BST(HYS) Gate drive UV hysteresis V(BST - SW) falling 200 mV
LOW-SIDE FET
RDS(ON) Low-side on resistance ISW = 0.5 A 0.24 Ω
HIGH-SIDE CURRENT LIMIT
ILIM (HS) High-side current limit threshold 1.3 1.61 1.9 A
TRES Current limit response time ILIM (HS)threshold detect to FET turn-off 100 ns
TOFF Current limit forced off-time FB = 0 V, VIN = 72 V 13 16.5 21 µs
TOFF1 Current limit forced off-time FB = 0.1 V, VIN = 72 V 10 13 17 µs
TOFF2 Current limit forced off-time FB = 1 V, VIN = 72 V 2 2.7 4.1 µs
LOW-SIDE CURRENT LIMIT
ISOURCE(LS) Sourcing current limit 1.3 1.6 1.9 A
ISINK(LS) Sinking current limit 3
DIODE EMULATION
VFPWM(LOW) FPWM input logic low VIN = 48 V 1 V
VFPWM(HIGH) FPWM input logic high VIN = 48 V 3
IZX Zero cross detect current FPWM = 0 (Diode emulation) 22.5 mA
REGULATION COMPARATOR
VREF FB regulation level VIN = 48 V 1.975 2 2.015 V
I(BIAS) FB input bias current VIN = 48 V 100 nA
ERROR CORRECTION AMPLIFIER & SOFT-START
GM Error amp transconductance FB = VREF (±) 10 mV 100 µA/V
IEA(SOURCE) Error amp source current FB = 1 V, SS = 1 V 7.5 10 12.5 µA
IEA(SINK) Error amp sink current FB = 5 V, SS = 2.25 V 7.5 10 12.5
V(SS-FB) VSS - VFB clamp voltage FB = 1.75 V, CSS= 1 nF 135 mV
ISS Softstart charging current SS = 0.5 V 7.5 10 12.5 µA
ENABLE/UVLO
VUVLO (TH) UVLO threshold EN/UVLO rising 1.195 1.24 1.272 V
IUVLO(HYS) UVLO hysteresis current EN/UVLO = 1.4 V 15 20 25 µA
VSD(TH) Shutdown mode threshold EN/UVLO falling 0.29 0.35 V
VSD(HYS) Shutdown threshold hysteresis EN/UVLO rising 50 mV
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 175 °C
TSD(HYS) Thermal shutdown hysteresis 20 °C
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.

6.6 Switching Characteristics(1)

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C for LM5161-Q1. Unless otherwise stated, VIN = 48 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MINIMUM OFF-TIME
TOFF-MIN Minimum off-Time, FB = 0 V 170 ns
TOFF-MIN Minimum off-Time, FB = 0 V, VIN = 4.5 V 200 ns
ON-TIME GENERATOR
TON Test 1 VIN = 24 V, RON = 100 kΩ 420 540 665 ns
TON Test 2 VIN = 48 V, RON = 100 kΩ 270 ns
TON Test 3 VIN = 8 V, RON = 100 kΩ 1150 1325 1500 ns
TON Test 4 VIN = 72V, RON = 150 kΩ 285 ns
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

6.7 Typical Characteristics

At TA = 25°C and applicable to LM5161-Q1 unless otherwise noted.
LM5161-Q1 eff_3v3_fpwm0_SNVU504.gif
VOUT= 3.3 V RON= 110 kΩ
FPWM = 0
Figure 1. Efficiency at 300 kHz
LM5161-Q1 EFF_12VOUT_fpwm1_ext_vs_intVcc_SNVU504.gif
VOUT = 12 V RON = 402 kΩ
FPWM = 0 L = 100 µH
Figure 3. Efficiency at 300 kHz
LM5161-Q1 LineReg_extVcc_fpwm1_SNVU504.gif
VOUT = 12 V RON = 300 kΩ
FPWM = 1 L = 100 µH
Figure 5. Line Regulation
LM5161-Q1 Icc_vcc_SNVU504.gif
VIN = 48 V
Figure 7. VCC vs. ICC
LM5161-Q1 cl_fb_SNVU504.gif
Figure 9. TOFF (ILIM) vs. VFB
LM5161-Q1 ONTIME_12V_5V_SNVU504.gif
Figure 11. TON vs. VIN
LM5161-Q1 SD_VIN_SNVU504.gif
Figure 13. Shutdown Current vs. VIN
LM5161-Q1 VRON_VIN_R1_SNVU504.gif
Figure 15. Voltage at RON pin vs. Input Voltage
LM5161-Q1 Ref_TEMP_SNVU504.gif
VIN = 48 V
Figure 17. Reference Voltage vs. Temperature
LM5161-Q1 SD_TEMP_SNVU504.gif
VIN = 48 V
Figure 19. Input Shutdown Current vs. Temperature
LM5161-Q1 CL_TEMP_SNVU504.gif
VIN = 48 V
Figure 21. Current Limit vs. Temperature
LM5161-Q1 FPWM_TEMP_SNVU504.gif
VIN = 48 V
Figure 23. FPWM Threshold vs. Temperature
LM5161-Q1 Eff_5V_300k_CCMvsDCM_SNVU504.gif
VOUT= 5 V RON= 169 kΩ
L=47 µH
Figure 2. Efficiency at 300 kHz
LM5161-Q1 eff_VIN_12Vout_fpwm1_SNVU504.gif
VOUT = 12 V RON = 402 kΩ
FPWM = 1 L = 100 µH
Figure 4. Efficiency at 300 kHz
LM5161-Q1 Vcc_VIN_SNVU504.gif
Figure 6. VCC vs. VIN
LM5161-Q1 ICCvsExtVCC_SNVU504.gif
IOUT = 1 A FPWM = 0
Figure 8. ICC vs. External VCC
LM5161-Q1 OnTime_VIN_SNVU504.gif
Figure 10. TON vs. VIN
LM5161-Q1 Fsw_vs_VIN_R1_SNVU504.gif
VOUT = 12 V
Figure 12. FSW vs. VIN
LM5161-Q1 Operating_VIN_SNVU504.gif
VFB = 3 V
Figure 14. IIN vs. VIN (Operating, Non Switching)
LM5161-Q1 GD_UVLO_TEMP_SNVU504.gif
VIN = 48 V
Figure 16. Gate Drive UVLO vs. Temperature
LM5161-Q1 OP_TEMP_SNVU504.gif
VIN = 48 V
Figure 18. Input Operating Current vs. Temperature
LM5161-Q1 Vcc_UVLO_TEMP_SNVU504.gif
VIN = 48 V
Figure 20. VCC UVLO vs. Temperature
LM5161-Q1 sinkCL_TEMP_SNVU504.gif
VIN = 48 V
Figure 22. Sink Current Limit vs. Temperature
LM5161-Q1 RDSON_TEMP_SNVU504.gif
ISW = 500 mA VIN = 48 V
Figure 24. Switch Resistance vs. Temperature