JAJSCQ2B November 2016 – June 2018 TPS54200 , TPS54201
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT SUPPLY | ||||||
VVIN | Input voltage range | 4.5 | 28 | V | ||
IOFF | Shutdown current | PWM = GND | 2 | 8.6 | µA | |
VVIN_UVLO | VIN undervoltage lockout | Rising VVIN | 3.83 | 4.2 | 4.47 | V |
Falling VVIN | 3.4 | 3.7 | 3.95 | |||
Hysteresis | 470 | mV | ||||
DIMMING (PWM PIN) | ||||||
VADIM | Analog dimming-mode threshold | Rising VPWM | 1.97 | 2.07 | 2.17 | V |
Falling VPWM | 1.8 | |||||
VPDIM | PWM dimming-mode threshold | Rising VPWM | 0.9 | 1 | 1.1 | V |
Falling VPWM | 0.8 | |||||
VPWM | Threshold to identify PWM duty cycle | Rising VPWM | 0.91 | 1 | 1.12 | V |
Falling VPWM | 0.5 | 0.63 | 0.72 | |||
VPWM_SHUTDOWN | Shutdown threshold | 0.35 | 0.55 | V | ||
FEEDBACK AND ERROR AMPLIFIER | ||||||
VFB1 | Feedback voltage in analog dimming mode | PWM = 3.3 V, SW duty cycle > 90% | 201 | 205 | 210 | mV |
VFB2 | Feedback voltage in PWM dimming mode | PWM = 1.5 V, SW duty cycle > 90% | 96 | 100 | 104 | mV |
BOOT PIN | ||||||
VBOOT_UVLO | BOOT-SW UVLO threshold | Rising | 2.1 | 2.33 | V | |
Falling | 2 | 2.2 | ||||
POWER STAGE | ||||||
RHSD | High-side FET on-resistance | VBOOT – VSW= 6 V | 150 | 259 | mΩ | |
RLSD | Low-side FET on-resistance | VVIN > 6 V | 70 | 120 | mΩ | |
CURRENT LIMIT | ||||||
ILIM_HS1 | High-side current limit 1 | Either one of the following conditions:
1. PWM dimming mode 2. Analog dimming mode and PWM duty cycle >25% |
2.4 | 3 | 3.6 | A |
ILIM_HS2 | High-side current limit 2 | Analog dimming mode and PWM duty cycle <25% | 1 | 1.4 | 1.8 | A |
ILIM_LS_SOURCE | Low-side source current limit | VVIN > 6 V | 2.3 | 3.3 | 4.4 | A |
ILIM_LS_SINK | Low-side sink current limit | VVIN > 6 V | 1.25 | 1.7 | 2.2 | A |
FAULT PROTECTION | ||||||
Thermal shutdown(1) | Rising temperature | 150 | 160 | 170 | °C | |
Hysteresis | 10 | °C | ||||
VOVP | Overvoltage protection | 1 | V | |||
VOCP | Overcurrent protection | 120% |