JAJSCQ6A December   2016  – June 2018 SN65DSI83-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Configurations and Multipliers
      2. 8.3.2 ULPS
      3. 8.3.3 LVDS Pattern Generation
      4. 8.3.4 Reset Implementation
      5. 8.3.5 Initialization Sequence
      6. 8.3.6 LVDS Output Formats
      7. 8.3.7 DSI Lane Merging
      8. 8.3.8 DSI Pixel Stream Packets
      9. 8.3.9 DSI Video Transmission Specifications
    4. 8.4 Programming
      1. 8.4.1 Local I2C Interface Overview
    5. 8.5 Register Maps
      1. 8.5.1 Control and Status Registers Overview
        1. 8.5.1.1 CSR Bit Field Definitions – ID Registers
          1. 8.5.1.1.1 Registers 0x00 – 0x08
            1. Table 4. Registers 0x00 – 0x08 Field Descriptions
        2. 8.5.1.2 CSR Bit Field Definitions – Reset and Clock Registers
          1. 8.5.1.2.1 Register 0x09
            1. Table 5. Register 0x09 Field Descriptions
          2. 8.5.1.2.2 Register 0x0A
            1. Table 6. Register 0x0A Field Descriptions
          3. 8.5.1.2.3 Register 0x0B
            1. Table 7. Register 0x0B Field Descriptions
          4. 8.5.1.2.4 Register 0x0D
            1. Table 8. Register 0x0D Field Descriptions
        3. 8.5.1.3 CSR Bit Field Definitions – DSI Registers
          1. 8.5.1.3.1 Register 0x10
            1. Table 9. Register 0x10 Field Descriptions
          2. 8.5.1.3.2 Register 0x11
            1. Table 10. Register 0x11 Field Descriptions
          3. 8.5.1.3.3 Register 0x12
            1. Table 11. Register 0x12 Field Descriptions
        4. 8.5.1.4 CSR Bit Field Definitions – LVDS Registers
          1. 8.5.1.4.1 Register 0x18
            1. Table 12. Register 0x18 Field Descriptions
          2. 8.5.1.4.2 Register 0x19
            1. Table 13. Register 0x19 Field Descriptions
          3. 8.5.1.4.3 Register 0x1A
            1. Table 14. Register 0x1A Field Descriptions
          4. 8.5.1.4.4 Register 0x1B
            1. Table 15. Register 0x1B Field Descriptions
        5. 8.5.1.5 CSR Bit Field Definitions – Video Registers
          1. 8.5.1.5.1  Register 0x20
            1. Table 16. Register 0x20 Field Descriptions
          2. 8.5.1.5.2  Register 0x21
            1. Table 17. Register 0x21 Field Descriptions
          3. 8.5.1.5.3  Register 0x24
            1. Table 18. Register 0x24 Field Descriptions
          4. 8.5.1.5.4  Register 0x25
            1. Table 19. Register 0x25 Field Descriptions
          5. 8.5.1.5.5  Register 0x28
            1. Table 20. Register 0x28 Field Descriptions
          6. 8.5.1.5.6  Register 0x29
            1. Table 21. Register 0x29 Field Descriptions
          7. 8.5.1.5.7  Register 0x2C
            1. Table 22. Register 0x2C Field Descriptions
          8. 8.5.1.5.8  Register 0x2D
            1. Table 23. Register 0x2D Field Descriptions
          9. 8.5.1.5.9  Register 0x30
            1. Table 24. Register 0x30 Field Descriptions
          10. 8.5.1.5.10 Register 0x31
            1. Table 25. Register 0x31 Field Descriptions
          11. 8.5.1.5.11 Register 0x34
            1. Table 26. Register 0x34 Field Descriptions
          12. 8.5.1.5.12 Register 0x36
            1. Table 27. Register 0x36 Field Descriptions
          13. 8.5.1.5.13 Register 0x38
            1. Table 28. Register 0x38 Field Descriptions
          14. 8.5.1.5.14 Register 0x3A
            1. Table 29. Register 0x3A Field Descriptions
          15. 8.5.1.5.15 Register 0x3C
            1. Table 30. Register 0x3C Field Descriptions
        6. 8.5.1.6 CSR Bit Field Definitions – IRQ Registers
          1. 8.5.1.6.1 Register 0xE0
            1. Table 31. Register 0xE0 Field Descriptions
          2. 8.5.1.6.2 Register 0xE1
            1. Table 32. Register 0xE1 Field Descriptions
          3. 8.5.1.6.3 Register 0xE5
            1. Table 33. Register 0xE5 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Video STOP and Restart Sequence
      2. 9.1.2 Reverse LVDS Pin Order Option
      3. 9.1.3 IRQ Usage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Example Script
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCORE Power Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Package Specific
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIL Low-level control signal input voltage 0.3 × VCC V
VIH High-level control signal input voltage 0.7 × VCC V
VOH High-level output voltage IOH = –4 mA 1.25 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
ILKG Input failsafe leakage current VCC = 0; VCC(PIN) = 1.8 V ±30 μA
IIH High level input current Any input terminal ±30 μA
IIL Low level input current Any input terminal ±30 μA
IOZ High-impedance output current CMOS output terminals ±10 μA
IOS Short-circuit output current Any output driving GND short ±50 mA
ICC Device active current See (2) 77 124 mA
IULPS Device standby current All data and clock lanes are in ultra-low power state (ULPS) 7.7 14 mA
IRST Shutdown current EN = 0 130 µA
REN EN control input resistor 200 kΩ
MIPI DSI INTERFACE
VIH-LP LP receiver input high threshold See Figure 2 880 mV
VIL-LP LP receiver input low threshold See Figure 2 550 mV
|VID| HS differential input voltage 100 270 mV
|VIDT| HS differential input voltage threshold 50 mV
VIL-ULPS LP receiver input low threshold; ultra-low power state (ULPS) 300 mV
VCM-HS HS common mode voltage; steady-state 70 330 mV
ΔVCM-HS HS common mode peak-to-peak variation including symbol delta and interference 100 mV
VIH-HS HS single-ended input high voltage See Figure 2 460 mV
VIL-HS HS single-ended input low voltage See Figure 2 –40 mV
VTERM-EN HS termination enable; single-ended input voltage (both Dp AND Dn apply to enable) Termination is switched simultaneous for Dn and Dp 450 mV
RDIFF-HS HS mode differential input impedance 80 125 Ω
LVDS OUTPUT
|VOD| Steady-state differential output voltage
A_Y x P/N		 CSR 0×19.3:2=00
100 Ω near end termination		 180 245 330 mV
CSR 0×19.3:2=01
100 Ω near end termination		 215 293 392
CSR 0×19.3:2=10
100 Ω near end termination		 250 341 455
CSR 0×19.3:2=11
100 Ω near end termination		 290 389 515
CSR 0×19.3:2=00
200 Ω near end termination		 150 204 275
CSR 0×19.3:2=01
200 Ω near end termination		 200 271 365
CSR 0×19.3:2=10
200 Ω near end termination		 250 337 450
CSR 0×19.3:2=11
200 Ω near end termination		 300 402 535
|VOD| Steady-state differential output voltage for
A_CLKP/N 		CSR 0×19.3:2=00
near end termination		 140 191 262 mV
CSR 0×19.3:2=01
100 Ω near end termination		 168 229 315
CSR 0×19.3:2=10
100 Ω near end termination		 195 266 365
CSR 0×19.3:2=11
100 Ω near end termination		 226 303 415
CSR 0×19.3:2=00
200 Ω near end termination		 117 159 220
CSR 0×19.3:2=01
200 Ω near end termination		 156 211 295
CSR 0×19.3:2=10
200 Ω near end termination		 195 263 362
CSR 0×19.3:2=11
200 Ω near end termination		 234 314 435
Δ|VOD| Change in steady-state differential output voltage between opposite binary states RL = 100 Ω 35 mV
VOC(SS) Steady state common-mode output voltage(3) CSR 0×19.6 = 1 and CSR 0×1B.6 = 1 Figure 3 0.75 0.9 1.13 V
CSR 0×19.6 = 0 see Figure 3 1 1.25 1.5
VOC(PP) Peak-to-peak common-mode output voltage see Figure 3 35 mV
RLVDS_DIS Pulldown resistance for disabled LVDS outputs 1 kΩ
(1) All typical values are at VCC = 1.8 V and TA = 25°C
(2) SN65DSI83-Q1: SINGLE Channel DSI to SINGLE Channel DSI, 1280 × 800
  • Number of LVDS lanes = 3 data lanes + 1 CLK lane
  • Number of DSI lanes = 4 data lanes + 1 CLK lane
  • LVDS CLK OUT = 83 M
  • DSI CLK = 500 M
  • RGB888, LVDS 18 bpp
Maximum values are at VCC = 1.95 V and TA = 85°C
(3) Tested at VCC = 1.8V , TA = –40°C for MIN, TA = 25°C for TYP, TA = 105°C for MAX.