JAJSD07C September   2016  – December 2022 DS90UB934-Q1

PRODUCTION DATA  

  1.   特長
  2. 1アプリケーション
  3. 2概要
  4. 3Revision History
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Electrical Characteristics
    6. 4.6 AC Electrical Characteristics
    7. 4.7 Recommended Timing for the Serial Control Bus
    8. 4.8 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Serial Frame Format
      2. 5.3.2 Line Rate Calculations for the DS90UB933/934
      3. 5.3.3 Deserializer Multiplexer Input
    4. 5.4 Device Functional Modes
      1. 5.4.1 RX MODE Pin
      2. 5.4.2 DVP Output Control
        1. 5.4.2.1 LOCK Status
      3. 5.4.3 Input Jitter Tolerance
      4. 5.4.4 Adaptive Equalizer
      5. 5.4.5 Channel Monitor Loop-Through Output Driver
        1. 5.4.5.1 Code Example for CMLOUT FPD3 RX Port 0:
      6. 5.4.6 GPIO Support
        1. 5.4.6.1 Back Channel GPIO
        2. 5.4.6.2 GPIO Pin Status
        3. 5.4.6.3 Other GPIO Pin Controls
        4. 5.4.6.4 FrameSync Operation
          1. 5.4.6.4.1 External FrameSync Control
          2. 5.4.6.4.2 Internally Generated FrameSync
            1. 5.4.6.4.2.1 Code Example for Internally Generated FrameSync
    5. 5.5 Programming
      1. 5.5.1 Serial Control Bus
        1. 5.5.1.1 I2C Target Operation
        2. 5.5.1.2 Remote Target Operation
        3. 5.5.1.3 Remote I2C Targets Data Throughput
        4. 5.5.1.4 Remote Target Addressing
        5. 5.5.1.5 Broadcast Write to Remote Target Devices
        6. 5.5.1.6 Code Example for Broadcast Write
      2. 5.5.2 Interrupt Support
        1. 5.5.2.1 Code Example to Enable Interrupts
        2. 5.5.2.2 FPD-Link III Receive Port Interrupts
        3. 5.5.2.3 Code Example to Readback Interrupts
        4. 5.5.2.4 Built-In Self Test (BIST)
          1. 5.5.2.4.1 BIST Configuration and Status
    6. 5.6 Register Maps
      1. 5.6.1 Register Description
      2. 5.6.2 Registers
      3. 5.6.3 Indirect Access Registers
      4. 5.6.4 Indirect Access Register Map
        1. 5.6.4.1 FPD3 Channel 0 Registers
        2. 5.6.4.2 FPD3 Channel 1 Registers
        3. 5.6.4.3 FPD3 RX Shared Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Over Coax
    3. 6.3 Typical Application
      1. 6.3.1 Design Requirements
      2. 6.3.2 Detailed Design Procedure
      3. 6.3.3 Application Curves
    4. 6.4 System Examples
    5. 6.5 Power Supply Recommendations
      1. 6.5.1 VDD Power Supply
      2. 6.5.2 Power-Up Sequencing
      3. 6.5.3 PDB Pin
      4. 6.5.4 Ground
    6. 6.6 Layout
      1. 6.6.1 Layout Guidelines
        1. 6.6.1.1 DVP Interface Guidelines
      2. 6.6.2 Layout Example
  9.   Mechanical, Packaging, and Orderable Information
  10. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Glossary
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 サポート・リソース
    5. 7.5 Trademarks
  11.   Mechanical, Packaging, and Orderable Information

4.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN OR FREQUENCYMINTYPMAXUNIT
TOTAL POWER CONSUMPTION
PTTotal Power Consumption normal operation
See Figure 4-5		Worst Case pattern
Default registers		V(VDD18) = V(VDDIO) = 1.89 V500685mW
V(VDD18) = 1.89 V,
V(VDDIO) = 3.6 V		9001125
SUPPLY CURRENT
IDDDeserializer Supply Current (includes load current). See Figure 4-5.f = 100 MHz, 10-bit mode
V(VDD18) = 1.89 V
Worst Case Pattern, Default Registers
CL = 8 pF		V(VDDIO) = 1.89 V OR 3.6 VVDD18250mA
V(VDDIO) = 1.89 VVDDIO60
V(VDDIO) = 3.6 VVDDIO145
f = 100 MHz, 12-bit HF mode
V(VDD18) = 1.89 V
Worst Case Pattern, Default Registers
CL = 8 pF		V(VDDIO) = 1.89 V OR 3.6 VVDD18270
V(VDDIO) = 1.89 VVDDIO90
V(VDDIO) = 3.6 VVDDIO170
f = 50 MHz, 12-bit LF mode
V(VDD18) = 1.89 V
Worst Case Pattern, Default Registers
CL = 8 pF		V(VDDIO) = 1.89 V OR 3.6 VVDD18240
V(VDDIO) = 1.89 VVDDIO80
V(VDDIO) = 3.6 VVDDIO155
IDDZDeserializer Power Down Supply CurrentV(VDD18) = 1.89 V, V(VDDIO) = 3.6V
PDB = L, All other LVCMOS inputs = 0V, Default Registers		VDD1830mA
VDDIO10
1.8-V LVCMOS I/O(1)
VOHHigh Level Output VoltageIOH = –2 mAV(VDDIO) = 1.71 V to 1.89 VROUT[11:0], HSYNC, VSYNC, LOCK, PASSV(VDDIO) – 0.45V(VDDIO)V
VOLLow Level Output VoltageIOL = 2 mAV(VDDIO) = 1.71 V to 1.89 VGND0.45V
VIHHigh Level Input VoltageV(VDDIO) = 1.71 V to 1.89 VGPIO[3:0], PDB, OEN, SEL, OSS_SEL, BISTEN0.65 ×
V(VDDIO)		V(VDDIO)V
VILLow Level Input VoltageV(VDDIO) = 1.71 V to 1.89 VGND0.35 ×
V(VDDIO)		V
IIHInput High CurrentVIN = 1.71 V to 1.89 VGPIO[3:0](4), OEN–2020μA
GPIO[2:0](5), SEL, PDB, OSS_SEL, BISTEN–100100
IILInput Low CurrentVIN = 0 VGPIO[3:0], PDB, OEN, SEL, OSS_SEL, BISTEN–2020μA
IOSOutput Short Circuit CurrentVOUT = 0 V–17mA
IOZTRI-STATE Output CurrentVOUT = 0 V or V(VDDIO), PDB = L–2020μA
3.3-V LVCMOS I/O(6)
VOHHigh Level Output VoltageIOH = –4 mAV(VDDIO) = 3.0 V to 3.6 VGPIO[3:0], ROUT[11:0], HSYNC, VSYNC, LOCK, PASS2.4V(VDDIO)V
VOLLow Level Output VoltageIOL = 4 mAV(VDDIO) = 3.0 V to 3.6 VGND0.4V
VIHHigh Level Input VoltageV(VDDIO) = 3.0 V to 3.6 VGPIO[3:0], OEN, SEL, OSS_SEL, BISTEN2V(VDDIO)V
PDB1.17V(VDDIO)
VILLow Level Input VoltageV(VDDIO) = 3.0 V to 3.6 VGPIO[3:0], OEN, SEL, OSS_SEL, BISTENGND0.8V
PDBGND0.63
IIHInput High CurrentVIN = 3.0 V to 3.6 VGPIO[3:0](4), OEN, PDB-2020μA
GPIO[2:0](5), SEL, OSS_SEL, BISTEN–190190
IILInput Low CurrentVIN = 0 VGPIO[3:0], OEN, SEL, OSS_SEL, BISTEN, PDB–2020μA
IOSOutput Short Circuit CurrentVOUT = 0 V–40mA
IOZTRI-STATE Output CurrentVOUT = 0 V or V(VDDIO), PDB = LOW–6060μA
I2C SERIAL CONTROL BUS(2)
VIHInput High LevelI2C_SDA, I2C_SCL0.7 × V(VDDIO)V(VDDIO)V
VILInput Low LevelGND0.3 × V(VDDIO)V
VHYInput Hysteresis50mV
VOLOutput Low LevelStandard/Fast Mode - IOL = 4 mA; Fast Plus Mode - IOL = 20 mA00.4V
IIHInput High CurrentVIN = V(VDDIO)–1010µA
IILInput Low CurrentVIN = 0V–1010µA
CINInput Capacitance(3)510pF
FPD-LINK III INPUT
VCMCommon Mode Voltage
See Figure 4-2.		1.2V
RTInternal Termination ResistorSingle Ended405060Ω
Differential80100120
FPD-LINK III BIDIRECTIONAL CONTROL CHANNEL
VOUT-BCBack Channel Single-Ended Output VoltageRL = 50 Ω, Coaxial configuration, forward channel disabledRIN0+, RIN1+190260mV
VOD-BCBack Channel Differential Output VoltageRL = 100 Ω, STP configuration, forward channel disabledRIN0+, RIN0–
RIN1+, RIN1–		380520mV
(1) V(VDDIO) = 1.8 V ± 5%
(2) V(VDDIO) = 1.8 V ± 5% OR 3.0 V to 3.6 V
(3) Specification is ensured by design and/or characterization and is not tested in production.
(1) The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream. The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.
(4) GPIO[2:0] Pulldown disabled; Register 0xBE = 0x03
(5) GPIO[2:0] Pulldown enabled; Register 0xBE = 0x00
(6) V(VDDIO) = 3.0 V to 3.6 V