JAJSD07C September   2016  – December 2022 DS90UB934-Q1

PRODUCTION DATA  

  1.   特長
  2. 1アプリケーション
  3. 2概要
  4. 3Revision History
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Electrical Characteristics
    6. 4.6 AC Electrical Characteristics
    7. 4.7 Recommended Timing for the Serial Control Bus
    8. 4.8 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Serial Frame Format
      2. 5.3.2 Line Rate Calculations for the DS90UB933/934
      3. 5.3.3 Deserializer Multiplexer Input
    4. 5.4 Device Functional Modes
      1. 5.4.1 RX MODE Pin
      2. 5.4.2 DVP Output Control
        1. 5.4.2.1 LOCK Status
      3. 5.4.3 Input Jitter Tolerance
      4. 5.4.4 Adaptive Equalizer
      5. 5.4.5 Channel Monitor Loop-Through Output Driver
        1. 5.4.5.1 Code Example for CMLOUT FPD3 RX Port 0:
      6. 5.4.6 GPIO Support
        1. 5.4.6.1 Back Channel GPIO
        2. 5.4.6.2 GPIO Pin Status
        3. 5.4.6.3 Other GPIO Pin Controls
        4. 5.4.6.4 FrameSync Operation
          1. 5.4.6.4.1 External FrameSync Control
          2. 5.4.6.4.2 Internally Generated FrameSync
            1. 5.4.6.4.2.1 Code Example for Internally Generated FrameSync
    5. 5.5 Programming
      1. 5.5.1 Serial Control Bus
        1. 5.5.1.1 I2C Target Operation
        2. 5.5.1.2 Remote Target Operation
        3. 5.5.1.3 Remote I2C Targets Data Throughput
        4. 5.5.1.4 Remote Target Addressing
        5. 5.5.1.5 Broadcast Write to Remote Target Devices
        6. 5.5.1.6 Code Example for Broadcast Write
      2. 5.5.2 Interrupt Support
        1. 5.5.2.1 Code Example to Enable Interrupts
        2. 5.5.2.2 FPD-Link III Receive Port Interrupts
        3. 5.5.2.3 Code Example to Readback Interrupts
        4. 5.5.2.4 Built-In Self Test (BIST)
          1. 5.5.2.4.1 BIST Configuration and Status
    6. 5.6 Register Maps
      1. 5.6.1 Register Description
      2. 5.6.2 Registers
      3. 5.6.3 Indirect Access Registers
      4. 5.6.4 Indirect Access Register Map
        1. 5.6.4.1 FPD3 Channel 0 Registers
        2. 5.6.4.2 FPD3 Channel 1 Registers
        3. 5.6.4.3 FPD3 RX Shared Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Over Coax
    3. 6.3 Typical Application
      1. 6.3.1 Design Requirements
      2. 6.3.2 Detailed Design Procedure
      3. 6.3.3 Application Curves
    4. 6.4 System Examples
    5. 6.5 Power Supply Recommendations
      1. 6.5.1 VDD Power Supply
      2. 6.5.2 Power-Up Sequencing
      3. 6.5.3 PDB Pin
      4. 6.5.4 Ground
    6. 6.6 Layout
      1. 6.6.1 Layout Guidelines
        1. 6.6.1.1 DVP Interface Guidelines
      2. 6.6.2 Layout Example
  9.   Mechanical, Packaging, and Orderable Information
  10. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Glossary
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 サポート・リソース
    5. 7.5 Trademarks
  11.   Mechanical, Packaging, and Orderable Information

3 Revision History

Changes from Revision B (October 2018) to Revision C (September 2022)

  • 文書全体にわたって表、図、相互参照の採番方法を更新Go
  • Added description for reprogramming VIH and VIL thresholds and changed VDDIO to VI2C (pin 25) Go
  • Added description for reprogramming VIH and VIL thresholds (pins 1 and 2) Go
  • Added I2C target Operation description updated from DS90UB954 datasheetGo
  • Added Remote target Operation information/description copied over from DS90UB954 data sheetGo
  • Added section on Remote I2C targets Data Throughput copied from the DS90UB954 data sheet.Go
  • Added section on Remote Target Addressing copied over from DS90UB954 data sheet.Go
  • Added broadcast write to remote target devices. Copied from DS90UB954 data sheet.Go
  • Added section for Code Example for Broadcast Write. Copied from DS90UB954 data sheet.Go
  • Added registers 0x3F to 0x43Go
  • Changed I/O to VDDIO and added VDDIO to register 0x0D bits 7 and 6Go
  • Added Indirect Access Registers Section Go
  • Added Indirect Access Register MapGo
  • Added FPD3 Channel 0 Registers tableGo
  • Added FPD3 Channel 1 Registers tableGo
  • Added FPD3 RX Shared Registers tableGo
  • Added reset information below power up sequencing figure. Copied from DS90UB914 data sheet.Go

Changes from Revision A (January 2017) to Revision B (October 2018)

  • Added that unused GPIOs can be left open or floatingGo
  • Added that PDB is internal pull down enabledGo
  • Added description for selecting pull up resistor for OSS_SELGo
  • Added description for selecting pull up resistor for OENGo
  • Removed S, PD type for RES (pin 44)Go
  • Removed S, PD type for RES (pin 43) and added it must be tied to GND. Go
  • Added PDB test conditions for the LVCMOS IO voltage parameter in the Absolute Maximum Ratings table Go
  • Changed typical LVCMOS low-to-high transition time value from: 2.5 ns to: 2 nsGo
  • Changed maximum LVCMOS low-to-high transition time value from: 4 ns to: 3 nsGo
  • Changed typical LVCMOS high-to-low transition time value from: 2.5 ns to: 2 ns Go
  • Changed maximum LVCMOS high-to-low transition time value from: 4 ns to: 3 ns Go
  • Changed receiver clock jitter test condition from: SSCG[3:0] = OFF to: SSCG[0] = OFFGo
  • Changed deserializer period jitter test condition from: SSCG[3:0] = OFF to: SSCG[0] = OFFGo
  • Changed deserializer cycle-to-cycle clock jitter test condition from: SSCG[3:0] = OFF to: SSCG[0] = OFFGo
  • Changed input jitter symbol from: TOLJIT to: TIJIT Go
  • Added reference to compatibility with DS90UB953-Q1/935-Q1 serializers Go
  • Added column for DS90UB953-Q1/935-Q1Go
  • Added clarification on input mode selection Go
  • Fixed typo in Figure 13 supply rail text Go
  • Changed pullup power supply node from VDDIO to V(I2C)Go
  • Removed pullup resistor recommendationGo
  • Updated description of clock frequency during BIST operationGo
  • Fixed typos in register mapsGo
  • Updated register "TYPE" column per legend Go
  • Fixed typo in register name.Go
  • Added Power Over Coax section Go
  • Updated return loss S11 values Go
  • Added STP typical connection diagram Go
  • Updated recommendation for common ground planeGo
  • Updated recommendation for bypass capacitorsGo
  • Updated typical bypass capacitor value from 50 uF to 47 uFGo

Changes from Revision * (September 2016) to Revision A (January 2017)

  • 「製品プレビュー」から「量産データ」に変更Go
  • Fixed broken link in Power Over Coax sectionGo