JAJSD52A March   2017  – December 2018 OPT3001-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
    2.     スペクトル応答： OPT3001-Q1および肉眼
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. 8.3.4.1 Serial Bus Address
        2. 8.3.4.2 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. 8.4.2.1 Latched Window-Style Comparison Mode
        2. 8.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 8.4.2.3 End-of-Conversion Mode
        4. 8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. 8.5.1.1 High-Speed I2C Mode
        2. 8.5.1.2 General-Call Reset Command
        3. 8.5.1.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
        1. 8.6.1.1 Register Descriptions
          1. 8.6.1.1.1 Result Register (offset = 00h)
            1. Table 7. Result Register Field Descriptions
          2. 8.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
            1. Table 10. Configuration Register Field Descriptions
          3. 8.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
            1. Table 11. Low-Limit Register Field Descriptions
          4. 8.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
            1. Table 13. High-Limit Register Field Descriptions
          5. 8.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
            1. Table 14. Manufacturer ID Register Field Descriptions
          6. 8.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
            1. Table 15. Device ID Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Optomechanical Design
        2. 9.2.2.2 Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 ハンダ付けと取り扱いについての推奨事項
    2. 13.2 DNP (S-PDSO-N6)メカニカル図面

7.5 Electrical Characteristics

At TA = 25°C, VDD = 3.3 V, (2), automatic full-scale range (RN[3:0] = 1100b(2)), white LED, and normal-angle incidence of light, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPTICAL
Peak irradiance spectral responsivity 550 nm
Resolution (LSB) Lowest full-scale range, RN[3:0] = 0000b at 800 ms conversion time (2) 0.01 lux
Lowest full-scale range, RN[3:0] = 0000b(1) at 100 ms conversion time 0.08
Full-scale illuminance 83 865.6 lux
Measurement output result 0.64 lux per ADC code, 2620.80 lux full-scale (RN[3:0] = 0110)(2), 2000 lux input(3) 2812 3125 3437 ADC codes
1800 2000 2200 lux
Relative accuracy between gain ranges(1) 0.2%
Infrared response (850 nm)(3) 0.2%
Light source variation
(incandescent, halogen, fluorescent)		 Bare device, no cover glass 4%
Linearity Input illuminance > 40 lux 2%
Input illuminance < 40 lux 5%
Measurement drift across temperature Input illuminance = 2000 lux 0.01 %/°C
Dark condition, ADC output For Conversion Time = 800 ms 0 3 ADC codes
For Conversion Time = 100 ms 0 1
Half-power angle 50% of full-power reading 47 degrees
PSRR Power-supply rejection ratio VDD at 3.6 V and 1.6 V 0.1 %/V(4)
POWER SUPPLY
VDD Operating range 1.6 3.6 V
VI²C Operating range of I2C pullup resistor I2C pullup resistor, VDD ≤ VI²C 1.6 5.5 V
IQ Quiescent current Dark Active, VDD = 3.6 V 1.8 2.5 µA
Shutdown (M[1:0] = 00)(2), VDD = 3.6 V 0.3 0.47 µA
Full-scale lux Active, VDD = 3.6 V 3.7 µA
Shutdown,
(M[1:0] = 00)(2) 		0.4 µA
POR Power-on-reset threshold TA = 25°C 0.8 V
DIGITAL
I/O pin capacitance 3 pF
Total integration time(5) (CT = 1)(2), 800-ms mode, fixed lux range 720 800 880 ms
(CT = 0)(2), 100-ms mode, fixed lux range 90 100 110 ms
VIL Low-level input voltage
(SDA, SCL, and ADDR)		 0 0.3 × VDD V
VIH High-level input voltage
(SDA, SCL, and ADDR)		 0.7 × VDD 5.5 V
IIL Low-level input current
(SDA, SCL, and ADDR)		 0.01 0.25(6) µA
VOL Low-level output voltage
(SDA and INT)		 IOL= 3 mA 0.32 V
IZH Output logic high, high-Z leakage current (SDA, INT) Pin at VDD 0.01 0.25(6) µA
TEMPERATURE
Specified temperature range Grade 2 –40 105 °C
Grade 3 –40 85 °C
(1) Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.
(2) Refers to a control field within the configuration register.
(3) Tested with the white LED calibrated to 2k lux and an 850-nm LED.
(4) PSRR is the percent change of the measured lux output from its current value, divided by the change in power supply voltage, as characterized by results from 3.6-V and 1.6-V power supplies.
(5) The conversion time, from start of conversion until the data are ready to be read, is the integration time plus 3 ms.
(6) The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller.