JAJSD52A March   2017  – December 2018 OPT3001-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
    2.     スペクトル応答： OPT3001-Q1および肉眼
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. 8.3.4.1 Serial Bus Address
        2. 8.3.4.2 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. 8.4.2.1 Latched Window-Style Comparison Mode
        2. 8.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 8.4.2.3 End-of-Conversion Mode
        4. 8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. 8.5.1.1 High-Speed I2C Mode
        2. 8.5.1.2 General-Call Reset Command
        3. 8.5.1.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
        1. 8.6.1.1 Register Descriptions
          1. 8.6.1.1.1 Result Register (offset = 00h)
            1. Table 7. Result Register Field Descriptions
          2. 8.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
            1. Table 10. Configuration Register Field Descriptions
          3. 8.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
            1. Table 11. Low-Limit Register Field Descriptions
          4. 8.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
            1. Table 13. High-Limit Register Field Descriptions
          5. 8.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
            1. Table 14. Manufacturer ID Register Field Descriptions
          6. 8.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
            1. Table 15. Device ID Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Optomechanical Design
        2. 9.2.2.2 Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 ハンダ付けと取り扱いについての推奨事項
    2. 13.2 DNP (S-PDSO-N6)メカニカル図面

8.6.1.1.1 Result Register (offset = 00h)

This register contains the result of the most recent light to digital conversion. This 16-bit register has two fields: a 4-bit exponent and a 12-bit mantissa.

Figure 27. Result Register (Read-Only)
15 14 13 12 11 10 9 8
E3 E2 E1 E0 R11 R10 R9 R8
R R R R R R R R
7 6 5 4 3 2 1 0
R7 R6 R5 R4 R3 R2 R1 R0
R R R R R R R R
LEGEND: R = Read only

Table 7. Result Register Field Descriptions

Bit Field Type Reset Description
15:12 E[3:0] R 0h Exponent.
These bits are the exponent bits. Table 8 provides further details.
11:0 R[11:0] R 000h Fractional result.
These bits are the result in straight binary coding (zero to full-scale).

Table 8. Full-Scale Range and LSB Size as a Function of Exponent Level

E3 E2 E1 E0 FULL-SCALE RANGE (lux) LSB SIZE (lux per LSB)
0 0 0 0 40.95 0.01
0 0 0 1 81.90 0.02
0 0 1 0 163.80 0.04
0 0 1 1 327.60 0.08
0 1 0 0 655.20 0.16
0 1 0 1 1310.40 0.32
0 1 1 0 2620.80 0.64
0 1 1 1 5241.60 1.28
1 0 0 0 10483.20 2.56
1 0 0 1 20966.40 5.12
1 0 1 0 41932.80 10.24
1 0 1 1 83865.60 20.48

The formula to translate this register into lux is given in Equation 1:

Equation 1. lux = LSB_Size × R[11:0]

where:

Equation 2. LSB_Size = 0.01 × 2E[3:0]

LSB_Size can also be taken from Table 8. The complete lux equation is shown in Equation 3:

Equation 3. lux = 0.01 × (2E[3:0]) × R[11:0]

A series of result register output examples with the corresponding LSB weight and resulting lux are given in Table 9. Note that many combinations of exponents (E[3:0]) and fractional results (R[11:0]) can map onto the same lux result, as shown in the examples of Table 9.

Table 9. Examples of Decoding the Result Register into lux

RESULT REGISTER
(Bits 15:0, Binary)		 EXPONENT
(E[3:0], Hex)		 FRACTIONAL RESULT
(R[11:0], Hex)		 LSB WEIGHT
(lux, Decimal)		 RESULTING LUX (Decimal)
0000 0000 0000 0001b 00h 001h 0.01 0.01
0000 1111 1111 1111b 00h FFFh 0.01 40.95
0011 0100 0101 0110b 03h 456h 0.08 88.80
0111 1000 1001 1010b 07h 89Ah 1.28 2818.56
1000 1000 0000 0000b 08h 800h 2.56 5242.88
1001 0100 0000 0000b 09h 400h 5.12 5242.88
1010 0010 0000 0000b 0Ah 200h 10.24 5242.88
1011 0001 0000 0000b 0Bh 100h 20.48 5242.88
1011 0000 0000 0001b 0Bh 001h 20.48 20.48
1011 1111 1111 1111b 0Bh FFFh 20.48 83865.60

Note that the exponent field can be disabled (set to zero) by enabling the exponent mask (configuration register, ME field = 1) and manually programming the full-scale range (configuration register, RN[3:0] < 1100b (0Ch)), allowing for simpler operation in a manually-programmed, full-scale mode. Calculating lux from the result register contents only requires multiplying the result register by the LSB weight (in lux) associated with the specific programmed full-scale range (see Table 8). See the Low-Limit Register for details.

See the configuration register conversion time field (CT, bit 11) description for more information on lux resolution as a function of conversion time.