10.2.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

• Output range of the potential transformers (elements labeled PT1, PT2, and PT3 in Figure 45)
• Output range of the current transformers (elements labeled CT1, CT2, and CT3 in Figure 45)
• Input impedance required from the analog front-end for each channel
• Fundamental frequency of the power system
• Number of harmonics that must be acquired, and
• Type of signal conditioning required from the analog front-end for each channel

10.2.2 Detailed Design Procedure

Figure 46 shows the topology chosen to meet the design requirements.

NOTE

A feedback capacitor C_F is included in order to provide a low-pass filter characteristic and attenuate signals outside the band of interest.

The potential transformers and current transformers used in the system depicted in Figure 45 provide the eight inputs required. These transformers have a ±10-V output range. Although the PT and CT elements provide isolation from the power system, the value of R_IN is selected as 100 kΩ in order to provide an additional, high-impedance safety element in the current path leading up to the input of the ADC. Moreover, selecting a low-frequency gain of –1 V/V (as shown in Equation 5) provides a ±10-V output that can be fed into the ADS8568; therefore, the value of R_F is selected as 100 kΩ too.

The primary goal of the acquisition system depicted in Figure 45 is to measure up to 20 harmonics in a 60-Hz power network. With this goal in mind, the analog front-end must have sufficient bandwidth to measure signals up to 1260 Hz as shown in Equation 6.

Based on the bandwidth from in Equation 6, the ADS8568 is set to simultaneously sample all six channels at 15.36 kSPS, thus providing enough samples to clearly resolve even the highest harmonic required.

The passband of the configuration shown in Figure 46 is determined by the –3-dB frequency according to Equation 7. The value of C_F is selected as 820 pF because C_F is a standard capacitance value available in 0603 size (surface-mount component) and such values, combined with that of R_F, result in sufficient bandwidth to accommodate the required 20 harmonics (at 60 Hz).

The value of R₁ is selected as the parallel combination of R_IN and R_F to prevent the input bias current of the operational amplifier from generating an offset error.

The value of component C₁ is chosen as 0.1 µF to provide a low-impedance path for noise signals that can be picked up by R₁, thus improving the EMI robustness and noise performance of the system.

The OPA2277 is chosen for its low input offset voltage, low drift, bipolar swing, sufficient gain-bandwidth product, and low quiescent current. For additional information on the procedure to select SAR ADC input drivers, see the TIPD151 verified design guide, 16-Bit 100-KSPS 4-Channel Multiplexed Data Acquisition System Design Guide.

The charge injection damping circuit is composed by R₂ (49.9 Ω) and C₂ (370 pF); these components reject high-frequency noise and meet the settling requirements of the ADS8568 input.

Figure 47 shows the reference block used in this design.

For more information on the design of charge injection damping circuits and reference driving circuits for SAR ADCs, see the TIPD149 verified design reference guide, Power-Optimized 16-Bit 1-MSPS Data Acquisition Block for Lowest Distortion and Noise.

10.2.3 Application Curve

Figure 48 shows the frequency spectrum of the data acquired by the ADS8568 for a sinusoidal, 20-V_PP input at 60 Hz.

The ac performance parameters are:

• SNR: 91.16 dB
• THD: –94.34 dB
• SNDR: 89.45 dB
• SFDR: 96.56 dB