JAJSD96A February 2017 – June 2017 ADS114S06 , ADS114S08
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | AVDD to AVSS | –0.3 | 5.5 | V |
AVSS to DGND | –2.8 | 0.3 | ||
DVDD to DGND | –0.3 | 3.9 | ||
IOVDD to DGND | –0.3 | 5.5 | ||
Analog input voltage | AINx, GPIOx, REFPx, REFNx, REFCOM | AVSS – 0.3 | AVDD + 0.3 | V |
Digital input voltage | CS, SCLK, DIN, DOUT/DRDY, DRDY, START, RESET, CLK |
DGND – 0.3 | IOVDD + 0.3 | V |
Input current | Continuous, AVSS-SW, REFN0, REFOUT | –100 | 100 | mA |
Continuous, all other pins except power-supply pins | –10 | 10 | ||
Temperature | Junction, TJ | 150 | °C | |
Storage, Tstg | –60 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
Analog power supply | AVDD to AVSS | 2.7 | 5.25 | V | ||
AVSS to DGND | –2.625 | 0 | 0.05 | |||
AVDD to DGND | 1.5 | 5.25 | ||||
Digital core power supply | DVDD to DGND | 2.7 | 3.6 | V | ||
Digital IO power supply | IOVDD to DGND | DVDD | 5.25 | V | ||
ANALOG INPUTS(1) | ||||||
V(AINx) | Absolute input voltage(2) | PGA bypassed | AVSS – 0.05 | AVDD + 0.05 | V | |
PGA enabled, gain = 1 to 16 | AVSS + 0.15 + |VINMAX|·(Gain – 1) / 2 | AVDD – 0.15 – |VINMAX|·(Gain –1) / 2 | ||||
PGA enabled, gain = 32 to 128 | AVSS + 0.15 + 15.5·|VINMAX| | AVDD – 0.15 – 15.5·|VINMAX| | ||||
VIN | Differential input voltage | VIN = VAINP – VAINN | –VREF / Gain | VREF / Gain | V | |
VOLTAGE REFERENCE INPUTS(3) | ||||||
VREF | Differential reference input voltage | VREF = V(REFPx) – V(REFNx) | 0.5 | AVDD – AVSS | V | |
V(REFNx) | Absolute negative reference voltage | Negative reference buffer disabled | AVSS – 0.05 | V(REFPx) – 0.5 | V | |
Negative reference buffer enabled | AVSS | V(REFPx) – 0.5 | V | |||
V(REFPx) | Absolute positive reference voltage | Positive reference buffer disabled | V(REFNx) + 0.5 | AVDD + 0.05 | V | |
Positive reference buffer enabled | V(REFNx) + 0.5 | AVDD | V | |||
EXTERNAL CLOCK SOURCE(4) | ||||||
fCLK | External clock frequency | 2 | 4.096 | 4.5 | MHz | |
Duty cycle | 40% | 50% | 60% | |||
GENERAL-PURPOSE INPUTS (GPIOs) | ||||||
Input voltage | AVSS – 0.05 | AVDD + 0.05 | V | |||
DIGITAL INPUTS (Other than GPIOs) | ||||||
Input voltage | DGND | IOVDD | V | |||
TEMPERATURE RANGE | ||||||
TA | Operating ambient temperature | –50 | 125 | °C |
THERMAL METRIC(1) | ADS114S06, ADS114S08 | UNIT | ||
---|---|---|---|---|
VQFN (RHB) | TQFP (PBS) | |||
32 PINS | 32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 45.2 | 75.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 28.3 | 17.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 15.8 | 28.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 15.7 | 28.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.3 | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||||
Absolute input current | PGA bypassed, AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V |
0.5 | nA | |||||
PGA enabled, all gains, V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX |
–2 | 0.1 | 2 | |||||
Absolute input current drift | PGA bypassed, AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V |
2 | pA/°C | |||||
PGA enabled, all gains, V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX |
2 | |||||||
Differential input current | PGA bypassed, VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF |
1 | nA/V | |||||
PGA enabled, all gains, VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain |
–1 | 0.02 | 1 | nA | ||||
Differential input current drift | PGA bypassed, VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF |
3 | pA/°C | |||||
PGA enabled, all gains, VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain |
1 | |||||||
PGA | ||||||||
Gain settings | 1, 2, 4, 8, 16, 32, 64, 128 |
|||||||
Startup time | Enabling the PGA in conversion mode | 190 | µs | |||||
SYSTEM PERFORMANCE | ||||||||
Resolution (no missing codes) | 16 | Bits | ||||||
DR | Data rate | 2.5, 5, 10, 16.6, 20, 50, 60, 100, 200, 400, 800, 1000, 2000, 4000 |
SPS | |||||
INL | Integral nonlinearity (best fit) | PGA bypassed, VCM = AVDD / 2 | 1 | 10 | ppmFSR | |||
PGA enabled, gain = 1 to 8, VCM = AVDD / 2 | 2 | 15 | ||||||
PGA enabled, gain = 16 to 128, VCM = AVDD / 2, TA = –40°C to +85°C |
3 | 15 | ||||||
VIO | Input offset voltage | TA = 25°C, PGA bypassed | –120 | 20 | 120 | µV | ||
TA = 25°C, PGA enabled, gain = 1 to 8 | –120 / Gain | 20 / Gain | 120 / Gain | |||||
TA = 25°C, PGA enabled, gain = 16 to 128 | –15 | 2 | 15 | |||||
TA = 25°C, PGA bypassed, after internal offset calibration | On the order of noisePP at the set DR and gain | |||||||
TA = 25°C, PGA enabled, gain = 1 to 128, after internal offset calibration | On the order of noisePP at the set DR and gain | |||||||
TA = 25°C, PGA bypassed, global chop enabled | –2 | 0.2 | 2 | |||||
TA = 25°C, PGA enabled, gain = 1 to 128, global chop enabled |
–2 | 0.2 | 2 | |||||
Offset drift | TA = –40°C to +85°C, PGA bypassed | –75 | 10 | 75 | nV/°C | |||
TA = –40°C to +85°C, PGA enabled, gain = 1 to 128 | –100 | 15 | 100 | |||||
PGA bypassed | –75 | 10 | 75 | |||||
PGA enabled, gain = 1 to 8 | –200 | 15 | 200 | |||||
PGA enabled, gain = 16 to 128 | –150 | 15 | 150 | |||||
PGA bypassed, global chop enabled | –10 | 2 | 10 | |||||
PGA enabled, gain = 1 to 128, global chop enabled | –10 | 2 | 10 | |||||
SYSTEM PERFORMANCE (continued) | ||||||||
Gain error(1) | TA = 25°C, PGA bypassed | 40 | 120 | ppm | ||||
TA = 25°C, PGA enabled, gain = 1 to 32 | 40 | 120 | ||||||
TA = 25°C, PGA enabled, gain = 64 and 128 | 40 | 200 | ||||||
Gain drift(1) | TA = –40°C to +85°C, PGA bypassed | 0.5 | 1 | ppm/°C | ||||
TA = –40°C to +85°C, PGA enabled, gain = 1 to 128 | 0.5 | 2 | ||||||
PGA bypassed | 0.5 | 1 | ||||||
PGA enabled, gain = 1 to 128 | 1 | 4 | ||||||
Noise (input-referred) | See the Noise Performance section | |||||||
NMRR | Normal-mode rejection ratio(2) | fIN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS, sinc3 filter |
88 | dB | ||||
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS, sinc3 filter, external fCLK = 4.096 MHz |
102 | |||||||
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS, low-latency filter |
79 | |||||||
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS, low-latency filter, external fCLK = 4.096 MHz |
95 | |||||||
fIN = 50 Hz (±1 Hz), DR = 50 SPS, sinc3 filter | 87 | |||||||
fIN = 50 Hz (±1 Hz), DR = 50 SPS, sinc3 filter, external fCLK = 4.096 MHz |
101 | |||||||
fIN = 60 Hz (±1 Hz), DR = 60 SPS, sinc3 filter | 89 | |||||||
fIN = 60 Hz (±1 Hz), DR = 60 SPS, sinc3 filter, external fCLK = 4.096 MHz |
105 | |||||||
CMRR | Common-mode rejection ratio | At dc | 110 | 120 | dB | |||
fCM = 50 Hz or 60 Hz (±1 Hz), DR = 2.5 SPS to 10 SPS, sinc3 filter |
120 | 130 | ||||||
fCM = 50 Hz or 60 Hz (±1 Hz), DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS, low-latency filter |
115 | 125 | ||||||
PSRR | Power-supply rejection ratio | AVDD at dc | 90 | 105 | dB | |||
AVDD at 50 Hz or 60 Hz | 100 | 115 | ||||||
DVDD at dc | 100 | 115 | ||||||
VOLTAGE REFERENCE INPUTS | ||||||||
Absolute input current | Reference buffers disabled, external VREF = 2.5 V, REFP1/REFN1 inputs |
-6 | 4 | 6 | µA/V | |||
Reference buffers enabled, external VREF = 2.5 V, REFP1/REFN1 inputs |
–15 | 5 | 15 | nA | ||||
INTERNAL VOLTAGE REFERENCE | ||||||||
VREF | Output voltage | 2.5 | V | |||||
Accuracy | TA = 25°C, TQFP package | –0.05% | ±0.01% | 0.05% | ||||
TA = 25°C, VQFN package | –0.1% | ±0.01% | 0.1% | |||||
Temperature drift | TA = –40°C to +85°C | 2.5 | 8 | ppm/°C | ||||
TA = –50°C to +125°C | 3 | 10 | ||||||
Output current | AVDD = 2.7 V to 3.3 V, sink and source | –5 | 5 | mA | ||||
AVDD = 3.3 V to 5.25 V, sink and source | –10 | 10 | ||||||
Short-circuit current limit | Sink and source | 70 | 100 | mA | ||||
PSRR | Power-supply rejection ratio | AVDD at dc | 85 | dB | ||||
Load regulation | AVDD = 2.7 V to 3.3 V, load current = –5 mA to 5 mA |
8 | µV/mA | |||||
AVDD = 3.3 V to 5.25 V, load current = –10 mA to 10 mA |
8 | |||||||
Startup time | 1-µF capacitor on REFOUT, 0.001% settling | 5.9 | ms | |||||
Capacitive load stability | Capacitor on REFOUT | 1 | 47 | µF | ||||
Reference noise | f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT | 9 | µVPP | |||||
INTERNAL OSCILLATOR | ||||||||
fCLK | Frequency | 4.096 | MHz | |||||
Accuracy | –1.5% | 1.5% | ||||||
EXCITATION CURRENT SOURCES (IDACS) | ||||||||
Current settings | 10, 50, 100, 250, 500, 750, 1000, 1500, 2000 |
µA | ||||||
Compliance voltage(3) | 10 µA to 750 µA, 0.1% deviation | AVSS | AVDD – 0.4 | V | ||||
1 mA to 2 mA, 0.1% deviation | AVSS | AVDD – 0.6 | ||||||
Accuracy (each IDAC) | TA = 25°C, 10 µA to 100 µA | –5% | ±0.7% | 5% | ||||
TA = 25°C, 250 µA to 2 mA | –3% | ±0.5% | 3% | |||||
Current mismatch between IDACs | TA = 25°C, 10 µA to 100 µA | 0.15% | 0.8% | |||||
TA = 25°C, 250 µA to 750 µA | 0.10% | 0.6% | ||||||
TA = 25°C, 1 mA to 2 mA | 0.07% | 0.4% | ||||||
Temperature drift (each IDAC) | 10 µA to 750 µA | 20 | 120 | ppm/°C | ||||
1 mA to 2 mA | 10 | 80 | ||||||
Temperature drift matching between IDACs | 10 µA to 100 µA | 3 | 25 | ppm/°C | ||||
250 µA to 2 mA | 2 | 15 | ||||||
Startup time | With internal reference already settled. From end of WREG command to current flowing out of pin. | 22 | µs | |||||
BIAS VOLTAGE | ||||||||
VBIAS | Output voltage settings | (AVDD + AVSS) / 2, (AVDD + AVSS) / 12 |
V | |||||
Output impedance | 350 | Ω | ||||||
Startup time | Combined capacitive load on all selected analog inputs CLOAD = 1 µF, 0.1% settling | 2.8 | ms | |||||
BURNOUT CURRENT SOURCES (BOCS) | ||||||||
Current settings | 0.2, 1, 10 | µA | ||||||
Accuracy | 0.2 µA, sinking or sourcing | ±8% | ||||||
1 µA, sinking or sourcing | ±4% | |||||||
10 µA, sinking or sourcing | ±2% | |||||||
PGA RAIL DETECTION | ||||||||
Positive rail threshold | Referred to the output of the PGA | AVDD – 0.15 | V | |||||
Negative rail threshold | Referred to the output of the PGA | AVSS + 0.15 | V | |||||
REFERENCE DETECTION | ||||||||
Threshold 1 | 0.3 | V | ||||||
Threshold 2 | 1/3·(AVDD – AVSS) | V | ||||||
Threshold 2 accuracy | –3% | ±1% | 3% | |||||
Pull-together resistance | 10 | MΩ | ||||||
SUPPLY VOLTAGE MONITORS | ||||||||
Accuracy | (AVDD – AVSS) / 4 monitor | ±1% | ||||||
DVDD / 4 monitor | ±1% | |||||||
TEMPERATURE SENSOR | ||||||||
Output voltage | TA = 25°C | 129 | mV | |||||
Temperature coefficient | 403 | µV/°C | ||||||
LOW-SIDE POWER SWITCH | ||||||||
RON | On-resistance | 1 | 3 | Ω | ||||
Current through switch | 75 | mA | ||||||
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs) | ||||||||
VIL | Logic input level, low | AVSS – 0.05 | 0.3 AVDD | V | ||||
VIH | Logic input level, high | 0.7 AVDD | AVDD + 0.05 | V | ||||
VOL | Logic output level, low | IOL = 1 mA | AVSS | 0.2 AVDD | V | |||
VOH | Logic output level, high | IOH = 1 mA | 0.8 AVDD | AVDD | V | |||
DIGITAL INPUT/OUTPUTS | ||||||||
VIL | Logic input level, low | DGND | 0.3 IOVDD | V | ||||
VIH | Logic input level, high | 0.7 IOVDD | IOVDD | V | ||||
VOL | Logic output level, low | IOL = 1 mA | DGND | 0.2 IOVDD | V | |||
VOH | Logic output level, high | IOH = 1 mA | 0.8 IOVDD | IOVDD | V | |||
Input current | DGND ≤ VDigital Input ≤ IOVDD | –1 | 1 | µA | ||||
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, External Reference, Internal Reference Disabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Flags Disabled, Internal Oscillator, All Data Rates, VIN = 0 V) | ||||||||
IAVDD | Analog supply current | Power-down mode | 0.1 | 1.5 | µA | |||
Standby mode, PGA bypassed | 70 | |||||||
Conversion mode, PGA bypassed | 85 | |||||||
Conversion mode, PGA enabled, gain = 1, 2 | 120 | 135 | ||||||
Conversion mode, PGA enabled, gain = 4, 8 | 140 | 155 | ||||||
Conversion mode, PGA enabled, gain = 16, 32 | 165 | 180 | ||||||
Conversion mode, PGA enabled, gain = 64 | 200 | |||||||
Conversion mode, PGA enabled, gain = 128 | 250 | |||||||
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V) | ||||||||
IAVDD | Analog supply current | Internal 2.5-V reference, no external load | 185 | 280 | µA | |||
Positive reference buffer | 35 | 60 | ||||||
Negative reference buffer | 25 | 40 | ||||||
VBIAS buffer, no external load | 10 | |||||||
IDAC overhead, 10 µA to 250 µA | 20 | 35 | ||||||
IDAC overhead, 500 µA to 750 µA | 30 | |||||||
IDAC overhead, 1 mA | 40 | |||||||
IDAC overhead, 1.5 mA | 50 | |||||||
IDAC overhead, 2 mA | 65 | |||||||
PGA rail detection and reference detection circuit | 10 | |||||||
DIGITAL SUPPLY CURRENT (DVDD = IOVDD = 3.3 V, All Data Rates, SPI Not Active) | ||||||||
IDVDD + IIOVDD | Digital supply current | Power-down mode, internal oscillator | 0.1 | µA | ||||
Standby mode, internal oscillator | 185 | |||||||
Conversion mode, internal oscillator | 225 | 300 | ||||||
Conversion mode, external fCLK = 4.096 MHz | 195 | |||||||
POWER DISSIPATION (AVDD = DVDD = IOVDD = 3.3 V, Internal Reference Enabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Flags Disabled, Internal Oscillator, All Data Rates, VIN = 0 V, SPI Not Active) | ||||||||
PD | Power dissipation | Conversion mode, PGA enabled, gain = 1 | 1.75 | mW |
MIN | MAX | UNIT(1) | ||
---|---|---|---|---|
SERIAL INTERFACE | ||||
td(CSSC) | Delay time, first SCLK rising edge after CS falling edge | 20 | ns | |
td(SCCS) | Delay time, CS rising edge after final SCLK falling edge | 20 | ns | |
tw(CSH) | Pulse duration, CS high | 30 | ns | |
tc(SC) | SCLK period | 100 | ns | |
tw(SCH) | Pulse duration, SCLK high | 40 | ns | |
tw(SCL) | Pulse duration, SCLK low | 40 | ns | |
tsu(DI) | Setup time, DIN valid before SCLK falling edge | 15 | ns | |
th(DI) | Hold time, DIN valid after SCLK falling edge | 20 | ns | |
td(CMD) | Delay time, between bytes or commands | 0 | ns | |
RESET PIN | ||||
tw(RSL) | Pulse duration, RESET low | 4 | tCLK | |
td(RSSC) | Delay time, first SCLK rising edge after RESET rising edge (or 7th SCLK falling edge of RESET command) | 4096 | tCLK | |
START/SYNC PIN | ||||
tw(STH) | Pulse duration, START/SYNC high | 4 | tCLK | |
tw(STL) | Pulse duration, START/SYNC low | 4 | tCLK | |
tsu(STDR) | Setup time, START/SYNC falling edge (or 7th SCLK falling edge of STOP command) before DRDY falling edge to stop further conversions (continuous conversion mode) | 32 | tCLK | |
READING CONVERSION DATA WITHOUT RDATA COMMAND | ||||
th(SCDR) | Hold time, SCLK low before DRDY falling edge(2) | 28 | tCLK | |
td(DRSC) | Delay time, SCLK rising edge after DRDY falling edge(2) | 4 | tCLK |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT(1) | |
---|---|---|---|---|---|---|
tp(CSDO) | Propagation delay time, CS falling edge to DOUT driven | 0 | 25 | ns | ||
tp(SCDO) | Propagation delay time, SCLK rising edge to valid new DOUT | 3 | 30 | ns | ||
tp(CSDOZ) | Propagation delay time, CS rising edge to DOUT high impedance | 0 | 25 | ns | ||
tp(STDR) | Propagation delay time, START/SYNC rising edge (or first SCLK rising edge of any command or data read) to DRDY rising edge | 2 | tCLK | |||
tw(DRH) | Pulse duration, DRDY high | 24 | tCLK | |||
tp(GPIO) | Propagation delay time, last SCLK falling edge of WREG command to GPIOx output valid | 3 | 100 | ns | ||
SPI timeout per 8 bit(2) | 215 | tCLK |
NOTE:
Single-byte communication is shown. Actual communication can be multiple bytes.NOTE:
Single-byte communication is shown. Actual communication can be multiple bytes.PGA bypassed, DR = 20 SPS, VIN = 0 V |
PGA enabled, gain = 1, DR = 20 SPS, VIN = 0 V |
PGA bypassed, DR = 20 SPS, VCM = 1.65 V |
PGA enabled, DR = 20 SPS, VCM = 1.65 V |
PGA bypassed, gain = 1 |
IDAC output voltage = 1.65 V |
Level 0 = 300 mV |
AVDD = 3.3 V |
DVDD = 3.3 V |
Standby and conversion mode, external VREF |
Power-down mode |
Standby and conversion mode |
Power-down mode |
PGA bypassed, DR = 4 kSPS, VIN = 0 V |
PGA enabled, gain = 1, DR = 4 kSPS, VIN = 0 V |
PGA bypassed, DR = 4 kSPS, VCM = 1.65 V |
PGA enabled, DR = 4 kSPS, VCM = 1.65 V |
PGA enabled, gain = 1 |
28 units, TQFP package |
28 units | ||
Level 1 = 1/3 · (AVDD – AVSS) |
AVDD = 3.3 V |
DVDD = 3.3 V |
Conversion mode, external VREF |
Conversion mode |