JAJSDB7B June   2017  – October 2021 TPS7A83A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: General
    6. 7.6 Electrical Characteristics: TPS7A8300A
    7. 7.7 Electrical Characteristics: TPS7A8301A
    8. 7.8 Typical Characteristics: TPS7A8300A
    9. 7.9 Typical Characteristics: TPS7A8301A
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Regulation Features
        1. 8.3.1.1 DC Regulation
        2. 8.3.1.2 AC and Transient Response
      2. 8.3.2 System Start-Up Features
        1. 8.3.2.1 Programmable Soft-Start (NR/SS)
        2. 8.3.2.2 Internal Sequencing
          1. 8.3.2.2.1 Enable (EN)
          2. 8.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 8.3.2.2.3 Active Discharge
        3. 8.3.2.3 Power-Good Output (PG)
      3. 8.3.3 Internal Protection Features
        1. 8.3.3.1 Foldback Current Limit (ICL)
        2. 8.3.3.2 Thermal Protection (Tsd)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Regulation
      2. 8.4.2 Disabled
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection
        1. 9.1.1.1 Adjustable Operation
        2. 9.1.1.2 ANY-OUT Programmable Output Voltage
        3. 9.1.1.3 ANY-OUT Operation
        4. 9.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
        5. 9.1.1.5 Recommended Capacitor Types
        6. 9.1.1.6 Input and Output Capacitor Requirements (CIN and COUT)
        7. 9.1.1.7 Feed-Forward Capacitor (CFF)
        8. 9.1.1.8 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      2. 9.1.2 Start Up
        1. 9.1.2.1 Soft-Start (NR/SS)
          1. 9.1.2.1.1 Inrush Current
        2. 9.1.2.2 Undervoltage Lockout (UVLO)
        3. 9.1.2.3 Power-Good (PG) Function
      3. 9.1.3 AC and Transient Performance
        1. 9.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 9.1.3.2 Output Voltage Noise
        3. 9.1.3.3 Optimizing Noise and PSRR
          1. 9.1.3.3.1 Charge Pump Noise
        4. 9.1.3.4 Load Transient Response
      4. 9.1.4 DC Performance
        1. 9.1.4.1 Output Voltage Accuracy (VOUT)
        2. 9.1.4.2 Dropout Voltage (VDO)
          1. 9.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 9.1.5 Sequencing Requirements
      6. 9.1.6 Negatively Biased Output
      7. 9.1.7 Reverse Current
      8. 9.1.8 Power Dissipation (PD)
        1. 9.1.8.1 Estimating Junction Temperature
        2. 9.1.8.2 Recommended Area for Continuous Operation (RACO)
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Models
        2. 12.1.1.2 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
8.3.2.2.1 Enable (EN)

The enable signal (VEN) is an active-high digital control that enables the LDO when the enable voltage is past the rising threshold (VEN ≥ VIH(EN)) and disables the LDO when the enable voltage is below the falling threshold (VEN ≤ VIL(EN)). The exact enable threshold is between VIH(EN) and VIL(EN) because EN is a digital control. Connect EN to VIN or VBIAS if enable functionality is not desired.