JAJSDB7B June   2017  – October 2021 TPS7A83A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: General
    6. 7.6 Electrical Characteristics: TPS7A8300A
    7. 7.7 Electrical Characteristics: TPS7A8301A
    8. 7.8 Typical Characteristics: TPS7A8300A
    9. 7.9 Typical Characteristics: TPS7A8301A
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Regulation Features
        1. 8.3.1.1 DC Regulation
        2. 8.3.1.2 AC and Transient Response
      2. 8.3.2 System Start-Up Features
        1. 8.3.2.1 Programmable Soft-Start (NR/SS)
        2. 8.3.2.2 Internal Sequencing
          1. 8.3.2.2.1 Enable (EN)
          2. 8.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 8.3.2.2.3 Active Discharge
        3. 8.3.2.3 Power-Good Output (PG)
      3. 8.3.3 Internal Protection Features
        1. 8.3.3.1 Foldback Current Limit (ICL)
        2. 8.3.3.2 Thermal Protection (Tsd)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Regulation
      2. 8.4.2 Disabled
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection
        1. 9.1.1.1 Adjustable Operation
        2. 9.1.1.2 ANY-OUT Programmable Output Voltage
        3. 9.1.1.3 ANY-OUT Operation
        4. 9.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
        5. 9.1.1.5 Recommended Capacitor Types
        6. 9.1.1.6 Input and Output Capacitor Requirements (CIN and COUT)
        7. 9.1.1.7 Feed-Forward Capacitor (CFF)
        8. 9.1.1.8 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      2. 9.1.2 Start Up
        1. 9.1.2.1 Soft-Start (NR/SS)
          1. 9.1.2.1.1 Inrush Current
        2. 9.1.2.2 Undervoltage Lockout (UVLO)
        3. 9.1.2.3 Power-Good (PG) Function
      3. 9.1.3 AC and Transient Performance
        1. 9.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 9.1.3.2 Output Voltage Noise
        3. 9.1.3.3 Optimizing Noise and PSRR
          1. 9.1.3.3.1 Charge Pump Noise
        4. 9.1.3.4 Load Transient Response
      4. 9.1.4 DC Performance
        1. 9.1.4.1 Output Voltage Accuracy (VOUT)
        2. 9.1.4.2 Dropout Voltage (VDO)
          1. 9.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 9.1.5 Sequencing Requirements
      6. 9.1.6 Negatively Biased Output
      7. 9.1.7 Reverse Current
      8. 9.1.8 Power Dissipation (PD)
        1. 9.1.8.1 Estimating Junction Temperature
        2. 9.1.8.2 Recommended Area for Continuous Operation (RACO)
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Models
        2. 12.1.1.2 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7.6 Electrical Characteristics: TPS7A8300A

over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V(1), OUT connected to 50 Ω to GND(2), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF, CNR/SS =0 nF, without CFF, and PG pin pulled up to VIN with 100 kohm, unless otherwise noted; Typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback voltage 0.8 V
VNR/SS NR/SS pin voltage 0.8 V
VOUT Output voltage Range Using the ANY-OUT pins 0.8 – 1.0% 3.95 + 1.0% V
Using external resistors(3) 0.8 – 1.0% 5.2 + 1.0%
Accuracy(3) (4) 0.8 V ≤ VOUT ≤ 5.2(5) V,
5 mA ≤ IOUT ≤ 2 A, over VIN 		–1.0% 1.0%
Accuracy with BIAS 1.1V ≤ VIN ≤ 2.2 V, 5 mA ≤ IOUT ≤ 2 A,
3.0 V ≤ VBIAS ≤ 6.5 V		 –0.75% 0.75%
ΔVOUT/
ΔVIN 		Line regulation IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.03 mV/V
ΔVOUT/
ΔIOUT 		Load regulation 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V,
VIN = 1.1 V		 0.07 mV/A
5 mA ≤ IOUT ≤ 2 A 0.08
5 mA ≤ IOUT ≤ 2 A, VOUT = 5.15 V 0.04
VDO Dropout voltage VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V – 3% 200 mV
VIN = 5.3 V, IOUT = 2 A, VFB = 0.8 V – 3% 200
VIN = 5.5 V, IOUT = 2 A, VFB = 0.8 V – 3% 300
VIN = 1.1 V, VBIAS = 5 V,
IOUT = 2 A, VFB = 0.8 V – 3%		 125
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V		 2.8 3.3 3.8 A
ISC Short-circuit current limit RLOAD = 20 mΩ, under foldback operation 1.0 A
PSRR Power-supply ripple rejection VIN – VOUT = 0.4 V,
IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF,
COUT = 22 μF		 f = 10 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V		 42 dB
f = 500 kHz, VOUT = 0.8 V, VBIAS = 5.0 V 39
f = 10 kHz,
VOUT = 5.0 V		 40
f = 500 kHz, VOUT = 5.0 V 25
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 2 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 22 μF		 4.4 μVRMS
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 2 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 22 μF		 7.7
IGND GND pin current VIN = 6.5 V, IOUT = 5 mA 2.8 4 mA
VIN = 1.4 V, IOUT = 2 A 3.7 5
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V 1.2 25 μA
VIT(PG) PG pin threshold For falling VOUT 82% . VOUT 88% . VOUT 93% . VOUT V
VHYS(PG) PG pin hysteresis For rising VOUT 2% . VOUT V
(1) VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the expected VOUT value set by the external feedback resistors.
(2) This 50-Ω load is disconnected when the test conditions specify an IOUT value.
(3) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(4) The device is not tested under conditions where VIN > VOUT + 1.7 V and IOUT = 3 A, because the power dissipation is higher than the maximum rating of the package.
(5) For VOUT ≤ 5 V, VIN = VOUT + 0.4 V; for VOUT > 5 V, VIN = VOUT + 0.45 V.