JAJSDJ8A April 2017 – October 2021 ADC12D1620QML-SP
PRODUCTION DATA
High-speed, high-performance ADCs such as the ADC12D1620 require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. The maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is found to be:
where
tJ(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: ADC input clock, system, input signals, and the ADC itself. Because the effective jitter added by the ADC is beyond user control, TI recommends keeping the sum of all other externally added jitter to a minimum.