JAJSDJ8A April 2017 – October 2021 ADC12D1620QML-SP
PRODUCTION DATA
The data is produced at the output at the same rate it is sampled at the input. The minimum recommended input clock rate for this device is fCLK(MIN); see Converter Electrical Characteristics: AC Electrical Characteristics. However, it is possible to operate the device in 1:2 demux mode and capture data from just one 12-bit bus; for example, just DI (or DId) although both DI and DId are fully operational. This decimates the data by two and effectively halves the data rate.