JAJSDJ8A April   2017  – October 2021 ADC12D1620QML-SP

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 6.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 6.7  Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
    8. 6.8  Converter Electrical Characteristic: Channel-to-Channel Characteristics
    9. 6.9  Converter Electrical Characteristics: LVDS CLK Input Characteristics
    10. 6.10 Electrical Characteristics: AutoSync Feature
    11. 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 6.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 6.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 6.14 Electrical Characteristics: Delta Parameters
    15. 6.15 Timing Requirements: Serial Port Interface
    16. 6.16 Timing Requirements: Calibration
    17. 6.17 Quality Conformance Inspection
    18. 6.18 Timing Diagrams
    19. 6.19 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Operation Summary
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Control and Adjust
        1. 7.3.1.1 AC- and DC-Coupled Modes
        2. 7.3.1.2 Input Full-Scale Range Adjust
        3. 7.3.1.3 Input Offset Adjust
        4. 7.3.1.4 Low-Sampling Power-Saving Mode (LSPSM)
        5. 7.3.1.5 DES Timing Adjust
        6. 7.3.1.6 Sampling Clock Phase Adjust
      2. 7.3.2 Output Control and Adjust
        1. 7.3.2.1 SDR / DDR Clock
        2. 7.3.2.2 LVDS Output Differential Voltage
        3. 7.3.2.3 LVDS Output Common-Mode Voltage
        4. 7.3.2.4 Output Formatting
        5. 7.3.2.5 Test-Pattern Mode
        6. 7.3.2.6 Time Stamp
      3. 7.3.3 Calibration Feature
        1. 7.3.3.1 Calibration Control Pins and Bits
        2. 7.3.3.2 How to Execute a Calibration
        3. 7.3.3.3 On-Command Calibration
        4. 7.3.3.4 Calibration Adjust
          1. 7.3.3.4.1 Read/Write Calibration Settings
        5. 7.3.3.5 Calibration and Power-Down
        6. 7.3.3.6 Calibration and the Digital Outputs
      4. 7.3.4 Power Down
      5. 7.3.5 Low-Sampling Power-Saving Mode (LSPSM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 DES/Non-DES Mode
      2. 7.4.2 Demux/Non-Demux Mode
    5. 7.5 Programming
      1. 7.5.1 Control Modes
        1. 7.5.1.1 Non-ECM
          1. 7.5.1.1.1  Dual-Edge Sampling Pin (DES)
          2. 7.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 7.5.1.1.3  Dual Data-Rate Phase Pin (DDRPh)
          4. 7.5.1.1.4  Calibration Pin (CAL)
          5. 7.5.1.1.5  Low-Sampling Power-Saving Mode Pin (LSPSM)
          6. 7.5.1.1.6  Power-Down I-Channel Pin (PDI)
          7. 7.5.1.1.7  Power-Down Q-Channel Pin (PDQ)
          8. 7.5.1.1.8  Test-Pattern Mode Pin (TPM)
          9. 7.5.1.1.9  Full-Scale Input-Range Pin (FSR)
          10. 7.5.1.1.10 AC- or DC-Coupled Mode Pin (VCMO)
          11. 7.5.1.1.11 LVDS Output Common-Mode Pin (VBG)
        2. 7.5.1.2 Extended Control Mode
          1. 7.5.1.2.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Driving the ADC in DES Mode
        3. 8.1.1.3 FSR and the Reference Voltage
        4. 8.1.1.4 Out-Of-Range Indication
        5. 8.1.1.5 AC-Coupled Input Signals
        6. 8.1.1.6 DC-Coupled Input Signals
        7. 8.1.1.7 Single-Ended Input Signals
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
        3. 8.1.3.3 Terminating Unused LVDS Output Pins
      4. 8.1.4 Synchronizing Multiple ADC12D1620 Devices in a System
        1. 8.1.4.1 AutoSync Feature
        2. 8.1.4.2 DCLK Reset Feature
      5. 8.1.5 Temperature Sensor
    2. 8.2 Radiation Environments
      1. 8.2.1 Total Ionizing Dose
      2. 8.2.2 Single Event Latch-Up and Functional Interrupt
      3. 8.2.3 Single Event Upset
    3. 8.3 Cold Sparing
  9. Power Supply Recommendations
    1. 9.1 System Power-On Considerations
      1. 9.1.1 Control Pins
      2. 9.1.2 Power On in Non-ECM
      3. 9.1.3 Power On in ECM
      4. 9.1.4 Power-on and Data Clock (DCLK)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Planes
      2. 10.1.2 Bypass Capacitors
      3. 10.1.3 Ground Planes
      4. 10.1.4 Power System Example
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Board Mounting Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Third-Party Products Disclaimer
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

Typical Characteristics

VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated.

GUID-B391938D-B17E-400F-9D50-5ED5F233DD84-low.pngFigure 6-11 INL vs Code
GUID-C0179588-EC71-4EB0-9115-3AD9A0D3FF77-low.pngFigure 6-13 DNL vs Code
GUID-E35438A5-4C59-4DB1-8D21-A1B1A25FE50B-low.gifFigure 6-15 ENOB vs Sample Rate
GUID-DB6E0D48-2F9E-477F-81F0-4CA4820BB686-low.gifFigure 6-17 ENOB vs Temperature
GUID-E79EE93B-A2B5-4384-BA4A-CF4268A94B8C-low.gifFigure 6-19 SNR vs Sample Rate
GUID-01CD56CC-1C42-4430-AC87-D261ED5679D8-low.gifFigure 6-21 SNR vs Temperature
GUID-7D3827E6-691C-4CF3-9674-016BBDF35BB0-low.gifFigure 6-23 THD vs Sample Rate
GUID-09F5BCF0-F31B-4F30-9201-5482AE93C6CF-low.gifFigure 6-25 THD vs Temperature
GUID-B4D16931-07F0-4447-A8B8-B2DD09C7B188-low.gifFigure 6-27 SFDR vs Sample Rate
GUID-A600AA3C-A78F-49AD-AA2E-CED99DA5D900-low.gifFigure 6-29 SFDR vs Temperature
GUID-23D59EE9-5044-40F3-BEF9-326E6ED79F12-low.gif
fCLK = 1.6 GHzfIN = 248 MHz
Figure 6-31 ENOB vs Temperature Calibration at 87.5°C Only
GUID-5346E0E2-B2FF-4CF8-AA8B-A2AF55082C93-low.gif
fCLK = 1.6 GHzfIN = 248 MHz
Figure 6-33 THD vs Temperature Calibration at 87.5°C Only
GUID-4F789BE2-FFA6-4E9D-981C-1958C951465F-low.gifFigure 6-35 3rd Order Intermodulation Distortion vs Input Frequency
GUID-943EF704-3AEA-46D7-BD19-70C685F66851-low.gifFigure 6-37 Cross Talk vs Input Frequency
GUID-04044A97-0A0B-4D9F-9BBD-9E273B828D42-low.pngFigure 6-39 Power Consumption vs Sample Rate
GUID-040AE460-D75B-4F42-AADB-8F923B26E41E-low.gifFigure 6-12 Minimum and Maximum INL vs Temperature
GUID-B79DCD0C-312A-4FA0-8B9E-9C5855ED85A9-low.gifFigure 6-14 Minimum and Maximum DNL vs Temperature
GUID-98CBE9D0-774F-4910-84FD-B4DD880A4CC0-low.gifFigure 6-16 ENOB vs Supply Voltage
GUID-B941EA36-6F2D-4EF8-98E1-84DD7BA9D2CD-low.gifFigure 6-18 ENOB vs Input Frequency
GUID-55B23E58-ECC2-4F0B-A0C6-CF7C7305DD23-low.gifFigure 6-20 SNR vs Supply Voltage
GUID-874568D1-ABE2-4309-A18C-971FE7CF97FB-low.gifFigure 6-22 SNR vs Input Frequency
GUID-C60EAC6F-B1B3-42F4-BB7E-366B239E2D74-low.gifFigure 6-24 THD vs Supply Voltage
GUID-CA147408-7B81-48BA-8DBF-0BC9D00C9C83-low.gifFigure 6-26 THD vs Input Frequency
GUID-C3280F2D-F68F-45AB-B700-CF03B654C2C6-low.gifFigure 6-28 SFDR vs Supply Voltage
GUID-D8688CDE-3D27-45F5-B2DC-F0A1CF09806A-low.gifFigure 6-30 SFDR vs Input Frequency
GUID-C6CE73CE-7C4B-4D25-A61A-0034A9675CAC-low.gif
fCLK = 1.6 GHzfIN = 248 MHz
Figure 6-32 SNR vs Temperature Calibration at 87.5°C Only
GUID-A103567F-DCB4-4D25-A471-C20D0CC08EE3-low.gif
fCLK = 1.6 GHzfIN = 248 MHz
Figure 6-34 SFDR vs Temperature Calibration at 87.5°C Only
GUID-B04429B6-B973-4E3E-A180-B8AE17445363-low.gifFigure 6-36 3rd Order Intermodulation Distortion vs Input Frequency (DES Mode 3200 MSPS)
GUID-295DF792-51E9-406A-BEEE-A5E519849544-low.gifFigure 6-38 Insertion Loss vs Input Frequency