JAJSDJ8A April 2017 – October 2021 ADC12D1620QML-SP
PRODUCTION DATA
The duty cycle of the input clock signal can affect the performance of any ADC. The ADC12D1620 device features a duty-cycle-clock correction circuit, which can maintain performance over the 20%-to-80% specified clock duty-cycle range. This feature is enabled by default and provides improved ADC clocking, especially in the dual-edge sampling (DES) mode.