JAJSDL3D March   2016  – October 2024 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics, Power Supply
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 HS Receive Equalization
      2. 6.3.2 HS TX Edge Rate Control
      3. 6.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 6.3.4 Dynamic De-skew
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 LP Mode
      3. 6.4.3 ULPS Mode
      4. 6.4.4 HS Mode
    5. 6.5 Register Maps
      1. 6.5.1  BIT Access Tag Conventions
      2. 6.5.2  Standard CSR Registers (address = 0x000 - 0x07)
      3. 6.5.3  Standard CSR Register (address = 0x08)
      4. 6.5.4  Standard CSR Register (address = 0x09)
      5. 6.5.5  Standard CSR Register (address = 0x0A)
      6. 6.5.6  Standard CSR Register (address = 0x0B)
      7. 6.5.7  Standard CSR Register (address = 0x0D)
      8. 6.5.8  Standard CSR Register (address = 0x0E)
      9. 6.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
      10. 6.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
  8. 7 Application and Implementation
    1. 7.1 Application Information,
    2. 7.2 Typical Application, CSI-2 Implementations
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Reset Implementation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.2 HS TX Edge Rate Control

The DPHY440 supports control of the rise and fall time for the DB[3:0]P/N and DBCP/N High Speed (HS) transmitters. Depending on system operating datarate, the HS edge rate may need to be adjusted to help improve EMI performance. The HS edge rate setting is determined through the sampled state of ERC/SDA pin at the rising edge of RSTN. If necessary, the HS edge rate can be adjusted by writing to the HS_ERC register via the local I2C interface.

Table 6-2 8.3.2 HS TX Edge Rate Control
ERC/SDA PINHS RISE/FALL TIMES
≤ VIL200 ps typical
VIM150 ps typical
≥ VIH250 ps typical

The DPHY440 also supports edge rate control for the LP interface. The adjustment of LP TX edge rate is determined by the state of the VSADJ_CFG0 and PRE_CFG1 pins as depicted in Table 6-3, but can also be modified by changing LP_ERC register through the local I2C interface