JAJSDL7D January   2016  – May 2021 TPS61194

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (1) (1)
    6. 6.6  Internal LDO Electrical Characteristics
    7. 6.7  Protection Electrical Characteristics
    8. 6.8  Current Sinks Electrical Characteristics
    9. 6.9  PWM Brightness Control Electrical Characteristics
    10. 6.10 Boost and SEPIC Converter Characteristics
    11. 6.11 Logic Interface Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated DC-DC Converter
      2. 7.3.2 Internal LDO
      3. 7.3.3 LED Current Sinks
        1. 7.3.3.1 Output Configuration
        2. 7.3.3.2 Current Setting
        3. 7.3.3.3 Brightness Control
      4. 7.3.4 Protection and Fault Detections
        1. 7.3.4.1 Adaptive DC-DC Voltage Control and Functionality of LED Fault Comparators
        2. 7.3.4.2 Overview of the Fault/Protection Schemes
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device States
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application for 4 LED Strings
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Input Capacitor Selection
          4. 8.2.1.2.4 LDO Output Capacitor
          5. 8.2.1.2.5 Diode
        3. 8.2.1.3 Application Curves
      2. 8.2.2 SEPIC Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Inductor
          2. 8.2.2.2.2 Diode
          3. 8.2.2.2.3 Capacitor C1
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8.2.2.2 Detailed Design Procedure

In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output voltage. Because of this, the maximum sum of input and output voltage must be limited below 50 V. See Detailed Design Procedure for general external component guidelines. Main differences of SEPIC compared to boost are described below.

Power Stage Designer™ Tool can be used for modeling SEPIC behavior: http://www.ti.com/tool/powerstage-designer. For detailed explanation on SEPIC see Texas Instruments Analog Applications Journal Designing DC/DC Converters Based on SEPIC Topology (SLYT309).