JAJSDL9B April   2017  – October 2017 LM36010

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Flash Mode
      2. 7.3.2 Torch Mode
      3. 7.3.3 IR Mode
    4. 7.4 Device Functioning Modes
      1. 7.4.1 Start-Up (Enabling The Device)
      2. 7.4.2 Pass Mode
      3. 7.4.3 Input Voltage Flash Monitor (IVFM)
      4. 7.4.4 Fault/Protections
        1. 7.4.4.1 Overvoltage Protection (OVP)
        2. 7.4.4.2 Input Voltage Flash Monitor (IVFM)
        3. 7.4.4.3 LED and/or VOUT Short Fault
        4. 7.4.4.4 Current Limit (OCP)
        5. 7.4.4.5 Thermal Scale-Back (TSB)
        6. 7.4.4.6 Thermal Shutdown (TSD)
        7. 7.4.4.7 Undervoltage Lockout (UVLO)
        8. 7.4.4.8 Flash Time-out (FTO)
    5. 7.5 Programming
      1. 7.5.1 Control Truth Table
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 I2C-Compatible Chip Address
    6. 7.6 Register Descriptions
      1. 7.6.1 Enable Register (0x01)
      2. 7.6.2 Configuration Register (0x02)
      3. 7.6.3 LED Flash Brightness Register (0x03)
      4. 7.6.4 LED Torch Brightness Register (0x04)
      5. 7.6.5 Flags Register (0x05)
      6. 7.6.6 Device ID and RESET Register (0x06)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Thermal Performance
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Inductor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

10 Layout

10.1 Layout Guidelines

The high switching frequency and large switching currents of the LM36010 make the choice of layout important. The following steps are to be used as a reference to ensure the device is stable and maintains proper LED current regulation across its intended operating voltage and current range.

  1. Place CIN on the top layer (same layer as the LM36010) and as close as possible to the device. The input capacitor conducts the driver currents during the low-side MOSFET turnon and turnoff and can detect current spikes over 1 A in amplitude. Connecting the input capacitor through short, wide traces to both the IN and GND pins reduces the inductive voltage spikes that occur during switching which can corrupt the VIN line.
  2. Place COUT on the top layer (same layer as the LM36010) and as close as possible to the OUT and GND pins. The returns for both CIN and COUT must come together at one point, as close as possible to the GND pin. Connecting COUT through short, wide traces reduce the series inductance on the OUT and GND pins that can corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
  3. Connect the inductor on the top layer close to the SW pin. There must be a low-impedance connection from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the SW node must be small so as to reduce the capacitive coupling of the high dV/dT present at SW that can couple into nearby traces.
  4. Avoid routing logic traces near the SW node so as to avoid any capacitively coupled voltages from SW onto any high-impedance logic lines such as STROBE, SDA, and SCL. A good approach is to insert an inner layer GND plane underneath the SW node and between any nearby routed traces. This creates a shield from the electric field generated at SW.
  5. Terminate the flash LED cathode directly to the GND pin of the LM36010. If possible, route the LED return with a dedicated path so as to keep the high amplitude LED current out of the GND plane. For a flash LED that is routed relatively far away from the LM36010, a good approach is to sandwich the forward and return current paths over the top of each other on two layers. This helps reduce the inductance of the LED current path.

10.2 Layout Example

LM36010 layout_boost.gif Figure 81. LM36010 Layout Example