JAJSDN8C March   2017  – April 2019 LMX2594

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reference Oscillator Input
      2. 8.3.2  Reference Path
        1. 8.3.2.1 OSCin Doubler (OSC_2X)
        2. 8.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 8.3.2.3 Programmable Multiplier (MULT)
        4. 8.3.2.4 Post-R Divider (PLL_R)
        5. 8.3.2.5 State Machine Clock
      3. 8.3.3  PLL Phase Detector and Charge Pump
      4. 8.3.4  N-Divider and Fractional Circuitry
      5. 8.3.5  MUXout Pin
        1. 8.3.5.1 Lock Detect
        2. 8.3.5.2 Readback
      6. 8.3.6  VCO (Voltage-Controlled Oscillator)
        1. 8.3.6.1 VCO Calibration
        2. 8.3.6.2 Determining the VCO Gain
      7. 8.3.7  Channel Divider
      8. 8.3.8  Output Buffer
      9. 8.3.9  Power-Down Modes
      10. 8.3.10 Phase Synchronization
        1. 8.3.10.1 General Concept
        2. 8.3.10.2 Categories of Applications for SYNC
        3. 8.3.10.3 Procedure for Using SYNC
        4. 8.3.10.4 SYNC Input Pin
      11. 8.3.11 Phase Adjust
      12. 8.3.12 Fine Adjustments for Phase Adjust and Phase SYNC
      13. 8.3.13 Ramping Function
        1. 8.3.13.1 Manual Pin Ramping
          1. 8.3.13.1.1 Manual Pin Ramping Example
        2. 8.3.13.2 Automatic Ramping
          1. 8.3.13.2.1 Automatic Ramping Example (Triangle Wave)
      14. 8.3.14 SYSREF
        1. 8.3.14.1 Programmable Fields
        2. 8.3.14.2 Input and Output Pin Formats
          1. 8.3.14.2.1 Input Format for SYNC and SysRefReq Pins
          2. 8.3.14.2.2 SYSREF Output Format
        3. 8.3.14.3 Examples
        4. 8.3.14.4 SYSREF Procedure
      15. 8.3.15 SysRefReq Pin
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Recommended Initial Power-Up Sequence
      2. 8.5.2 Recommended Sequence for Changing Frequencies
      3. 8.5.3 General Programming Requirements
    6. 8.6 Register Maps
      1. 8.6.1  General Registers R0, R1, & R7
        1. Table 24. Field Descriptions
      2. 8.6.2  Input Path Registers
        1. Table 25. Field Descriptions
      3. 8.6.3  Charge Pump Registers (R13, R14)
        1. Table 26. Field Descriptions
      4. 8.6.4  VCO Calibration Registers
        1. Table 27. Field Descriptions
      5. 8.6.5  N Divider, MASH, and Output Registers
        1. Table 28. Field Descriptions
      6. 8.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 29. Field Descriptions
      7. 8.6.7  Lock Detect Registers
        1. Table 30. Field Descriptions
      8. 8.6.8  MASH_RESET
        1. Table 31. Field Descriptions
      9. 8.6.9  SysREF Registers
        1. Table 32. Field Descriptions
      10. 8.6.10 CHANNEL Divider Registers
        1. Table 33. Field Descriptions
      11. 8.6.11 Ramping and Calibration Fields
        1. Table 34. Field Descriptions
      12. 8.6.12 Ramping Registers
        1. 8.6.12.1 Ramp Limits
          1. Table 35. Field Descriptions
        2. 8.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 36. Field Descriptions
        3. 8.6.12.3 Ramping Configuration
          1. Table 37. Field Descriptions
      13. 8.6.13 Readback Registers
        1. Table 38. Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 OSCin Configuration
      2. 9.1.2 OSCin Slew Rate
      3. 9.1.3 RF Output Buffer Power Control
      4. 9.1.4 RF Output Buffer Pullup
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

4 改訂履歴

Changes from B Revision (March 2018) to C Revision

  • Deleted the recommended bypass capacitor values for Vcc pins 7, 11, 15, 21, 26 and 37, as these capacitor values are not mandatory and the power supply filtering design is up to the user.Go
  • Changed all the 'FRAC_ORDER' to 'MASH_ORDER' to avoid confusionGo
  • Changed the names of timing specs to align with timing diagram: changed tCE to tES, tCS to tDCS, tCH to tCDH, and tCES to tECSGo
  • Changed the names of timing specs to align with timing diagram: changed tES to tCE, tCES to tECS, added tDCS and tCDH, and changed tCS to tCRGo
  • Changed the serial data input timing diagram and corrected the typo for 'SCK'Go
  • Deleted the note 'The CSB transition from high to low must occur when SCK is low' from the serial data input timing diagram, because SPI mode 4 (CPOL = 1, CPHA = 1) is also supported, and SCK is held high when idle in mode 4Go
  • Added note for the serial data input timing diagram to explain the tCE requirement for mode 4 (CPOL = 1, CPHA = 1) of SPI, because the diagram only indicated SPI mode 1 (CPOL = 0, CPHA = 0)Go
  • Changed the serial data readback timing diagramGo
  • Changed the note about MUXout clocking out and emphasized the effect of tCR on the readback data available timeGo
  • Changed the fOUT test conditions in the Closed-Loop Phase Noise at 3.5 GHz graph from: 14 GHz / 2 = 3.5 GHz to: to 14 GHz / 4 = 3.5 GHz Go
  • Added Normalized Output Power Across OUTA_PWR With Resistor Pullup graphGo
  • Changed "Vtune" to "Indirect Vtune" when LD_TYPE = 1Go
  • Changed description for LD_TYPE. Go
  • Added description of Indirect Vtune. Go
  • Added description for the 'no assist' mode, mphasized the effect of VCO_SEL, VCO_DACISET_STRT and VCO_CAPCTRL_STRT under 'no assist' mode, and added recommended values for these registersGo
  • Added description for the 'full assist' mode to allow the user to set VCO amplitude and capcode using linear interpolation under certain conditionsGo
  • Changed OUTx_PWR Recommendations for Resistor Pullup table Go
  • Added description for category 3 of SYNC feature stating that FCAL_EN needs to be 1.Go
  • Changed description of MASH_SEED Go
  • Added 10-ms wait time before re-programming register R0 in recommended initial power-up sequence Go
  • Added the General Programming Requirements section based on frequently asked questionsGo
  • Changed register R4 in the register map to: exposed ACAL_CMP_DLY Go
  • Changed the register R20[14] value from 0 to 1 in the full register map to match the R20 register description Go
  • Changed the default value of R25 to align with register map of LMX2595. This change has no impact on the LMX2594Go
  • Changed the R0[14] register field name in the register map from VCO_PHASE_SYNC_EN to VCO_PHASE_SYNC. to align with the rest of the data sheetGo
  • Added recommended value for register CAL_CLK_DIV when lock time is not of concernGo
  • Changed the typo for register 'VCO_DACISET' in the register map. Bit 0 of this register was not included in the map. The full register map and register description were correctGo
  • Added description to the R4[15:8]: ACAL_CMP_DLY registerGo
  • Deleted the bit description '0: disabled; 1: enabled' for register 'PLL_N'Go
  • Added description to the R60[15:0] LD_DLY registerGo
  • Changed the R31[14] register name from CHDIV_DIV2 to SEG1_EN to align with the naming in the TICS Pro GUIGo
  • Changed the R105[1:0] field name from RAMP_NEXT_TRIG to RAMP1_NEXT_TRIGGo
  • Added the Bias Levels of Pins tableGo

Changes from A Revision (August 2017) to B Revision

  • Changed all the VCO Gain typical values in the Electrical Characteristics table. This is due to improved measurement methods and NOT a change in the device itselfGo
  • Moved the high-level output voltage parameter VCC – 0.4 value from the MAX column to the MINGo
  • Moved the high-level output current parameter 0.4 value from the MIN column to the MAXGo
  • Changed bulleted text: data is clocked out on MUXout, not SDI pinGo
  • Added comment that OSCin is clocked on rising edges of the signal. and reformatted with bulleted listGo
  • Added description of the state machine clock Go
  • Changed example from: 200 MHz / 232 to: 200 MHz / (232 – 1) Go
  • Changed LD_DLY description in Table 4 and removed duplicated text in the Lock Detect sectionGo
  • Changed name from VCO_AMPCAL to VCO_DACISET_STRT Go
  • Added more programmable settings to Table 5Go
  • Changed VCO Gain tableGo
  • Added that OUTx_PWR states 32 to 47 are redundant and reworded sectionGo
  • Added term "IncludedDivide" for clarity Go
  • Changed Fixed Diagram to show SEG0, SEG1, SEG2, and SEG3 Go
  • Changed included channel divide to IncludedDivide and 2 X SEG0 to 2 X SEG1. Also clarified IncludedDivide calculationsGo
  • Added more description on conditions for phase adustGo
  • Changed text from: (VCO_PHASE_SYNC = 1) to: (VCO_PHASE_SYNC = 0) Go
  • Changed text so the user does not incorrectly assume that MASH_SEED varies from part ot partGo
  • Changed the RAMP_THRESH programming from: 0 to ± 232 to: 0 to ± 233 – 1Go
  • Removed comment that RAMP_TRIG_CAL only applies in automatic ramping modeGo
  • Changed the RAMP_LOW and _HIGH programming from: 0 to ± 231 to: 0 to ± 233 – 1Go
  • Changed description to be in terms of state machine cyclesGo
  • Changed RAMP_MODE to RAMP_MANUAL in the Manual Pin Ramping and Automatic Ramping sectionsGo
  • Added that the RampCLK pin input is reclocked to the phase detector frequencyGo
  • Added that RampDir rising edges should be targeted away from rising edges of RampCLK pinGo
  • Changed programming enumerations for RAMP0_INC and RAMP1_INCGo
  • Changed programming enumerations for RAMP_THRESH, RAMPx_LEN, and RAMP1_INCGo
  • Changed Figure 29Go
  • Changed SysRef descriptionGo
  • Added divide by 2 to figureGo
  • Changed some entries in the table Go
  • Changed fINTERPOLATOR SYSREF setup equation in Table 18Go
  • Changed SysRef delay from: 224 and 225 to: 225 and 226Go
  • Changed "generator" mode to "master" mode. They mean the same thingGo
  • Changed description for SYSREF_DIVGo
  • Changed Figure 31Go
  • Changed wording for repeater mode and master modeGo
  • Changed description of a few of the stepsGo
  • Changed typo in R17 and R19 Go
  • Deleted reference to VCO_SEL_STRT_EN. This is always 1Go
  • Added VCO_SEL_STRT_EN reference. This is always 1Go
  • Changed the enumerations 0-3 and added content to the INPIN_LVL field description Go
  • Added Divide by 1' to SYSREF_DIV_PRE register description. Also fixed the name misspellingGo
  • Deleted redundant formula for Fout and also clarified SYSREF_DIV starts at 4 and counts by 2Go
  • Deleted reference to VCO_CAPCTRL_EN, which is always 1, and clarifiedGo
  • Changed text from: fMAX to: fHIGHGo
  • Changed text from: RAMP_LIMIT_LOW=232 - (fLOW - fVCO) / fPD × 16777216 to: RAMP_LIMIT_LOW=233 - 16777216 x (fVCO - fLOW) / fPDGo
  • Removed the OSCin Configuration table and added content to the OSCin Configuration sectionGo
  • Changed pin 27 recommendation from 10 µF to 1 µF in Figure 51Go

Changes from * Revision (March 2017) to A Revision

  • Added DAP pin described as "Die Attach Pad"Go
  • Added H2 Spec for 11 GHz Go
  • Changed "SDA" pin name mispelled. Should be "SDI". Also fixed in timing diagrams. Also added CE Pin Go
  • Clarified that output power assumes that load is matched and losses are de-embeddedGo
  • Swapped SDI and SCK in diagram Go
  • Added graphs and reordered Go
  • Added 12-GHz VCO frequency for PLL Noise Metrics Plot Go
  • Added Phase Noise plots vs. Temperature Go
  • Added Phase noise vs. Fpd Graph Go
  • Moved second paragraph of Readback into Lock Detect section; deleted last paragraph of Readback (was in wrong place)Go
  • Changed table to allow 11.5 GHz max frequency for divides >6Go
  • Added Recommendations table Go
  • Changed the IncludedDivide tableGo
  • Added section on fine tune adjustments Go
  • Changed graphic and descriptionGo
  • Added SYSREF_EN = 1 if and only if OUTB_MUX=2 Go
  • Changed SysRef Example Description and Pictures Go
  • Added recommendation to make fInterpolator a multiple of fOSCGo
  • Added SEG1_ENGo
  • Added INPIN_IGNORE, INPIN_LVL, and INPIN_HYSTGo
  • Removed RAMP0_FL from register mapGo
  • Changed address for VCO_DACISET_STRT and VCO_CAPCTRL Go
  • Clarified MASH_RESET_N. 0 = RESET (integer mode), 1 = Fractional mode Go
  • Changed OUT_ISEL to OUTI_SET Go
  • Added SYSREF_EN=1 when OUTB_MUX=2 Go
  • Added section for input register descriptions Go
  • Added description for SEG1_EN Go
  • Fixed TYPO table to match main register map.Go
  • Added SEG1_ENGo
  • Corrected RAMP_BURST_TRIG description to match other place in data sheetGo
  • Removed duplicate error in R101[2] Go
  • Changed RAMP1_INC from RAMP0 to RAMP1Go
  • Clarified that the delay was in state machine cyclesGo
  • Swapped 1 and 3 in the R110[10:9] descriptionGo
  • Fixed pin names in schematic Go