JAJSDR0A July   2017  – September 2017 TPS7A39

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Startup Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 User-Settable Buffered Reference
      3. 7.3.3 Active Discharge
      4. 7.3.4 System Start-Up Controls
        1. 7.3.4.1 Start-Up Tracking
        2. 7.3.4.2 Sequencing
          1. 7.3.4.2.1 Enable (EN)
          2. 7.3.4.2.2 Undervoltage Lockout (UVLO) Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Setting the Output Voltages on Adjustable Devices
      2. 8.1.2  Capacitor Recommendations
      3. 8.1.3  Input and Output Capacitor (CINx and COUTx)
      4. 8.1.4  Feed-Forward Capacitor (CFFx)
      5. 8.1.5  Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      6. 8.1.6  Buffered Reference Voltage
      7. 8.1.7  Overriding Internal Reference
      8. 8.1.8  Start-Up
        1. 8.1.8.1 Soft-Start Control (NR/SS)
          1. 8.1.8.1.1 In-Rush Current
        2. 8.1.8.2 Undervoltage Lockout (UVLOx) Control
      9. 8.1.9  AC and Transient Performance
        1. 8.1.9.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.9.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 8.1.9.3 Output Voltage Noise
        4. 8.1.9.4 Optimizing Noise and PSRR
        5. 8.1.9.5 Load Transient Response
      10. 8.1.10 DC Performance
        1. 8.1.10.1 Output Voltage Accuracy (VOUTx)
        2. 8.1.10.2 Dropout Voltage (VDO)
      11. 8.1.11 Reverse Current
      12. 8.1.12 Power Dissipation (PD)
        1. 8.1.12.1 Estimating Junction Temperature
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Single-Ended to Differential Isolated Supply
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Switcher Choice
          2. 8.2.1.2.2 Full Bridge Rectifier With Center-Tapped Transformer
          3. 8.2.1.2.3 Total Solution Efficiency
          4. 8.2.1.2.4 Feedback Resistor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Getting the Full Range of a SAR ADC
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Detailed Design Description
          1. 8.2.2.3.1 Regulation of -0.2 V
          2. 8.2.2.3.2 Feedback Resistor Selection
        4. 8.2.2.4 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Package Mounting
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価モジュール
        2. 11.1.1.2 SPICEモデル
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

5 Pin Configuration and Functions

DSC Package
10-Pin WSON
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 INP I Positive input. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section for more information.
2 EN I Enable pin. Driving this pin to logic high (VEN ≥ VIH(EN)) enables the device; driving this pin to logic low (VEN ≤ VIL(EN)) disables the device. If enable functionality is not required, this pin must be connected to INP; see the Application and Implementation section for more detail. The enable voltage cannot exceed the input voltage (VEN ≤ VINP).
3 NR/SS — Noise-reduction, soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and enables soft-start and start-up tracking. A 10-nF or larger capacitor (CNR/SS) is recommended to be connected from NR/SS to GND to maximize or optimize ac performance and to ensure start-up tracking. This pin can also be driven externally to provide greater output voltage accuracy and lower noise, see the User-Settable Buffered Reference section for more information.
4 GND — Ground pin. This pin must be connected to ground and the thermal pad with a low-impedance connection.
5 INN I Negative input. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section for more information.
6 OUTN O Negative output. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the output capacitor as close to the output as possible; see the Capacitor Recommendations section for more information.
7 FBN I Negative output feedback pin. This pin is used to set the negative output voltage. Although not required, a 10-nF feed-forward capacitor from FBN to OUTN (as close to the device as possible) is recommended to maximize ac performance. Nominally this pin is regulated to VFBN. Do not connect to ground.
8 BUF O Buffered reference output. This pin is connected to FBN through R2 and the voltage at this node is inverted and scaled up by the negative feedback network to provide the desired output voltage. The buffered reference can be used to drive external circuits, and has a 1-mA maximum load.
9 FBP I Positive output feedback pin. This pin is used to set the positive output voltage. Although not required, a 10-nF feed-forward capacitor from FBP to OUTP (as close to the device as possible) is recommended to maximize ac performance. Nominally this pin is regulated to VFBP. Do not connect this pin directly to ground.
10 OUTP O Positive output. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the output capacitor as close to the output as possible; see the Capacitor Recommendations section for more information.
Pad Thermal Pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
(1) The nominal input and output capacitance must be greater than 2.2 µF; throughout this document the nominal derating on these capacitors is 80%. Take care to ensure that the effective capacitance at the pin is greater than 2.2 µF.