JAJSDV0J September   2017  – August 2023 TPS7B82-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Grade 1 Options
    6. 6.6 Electrical Characteristics: Grade 0 Options
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Undervoltage Shutdown
      3. 7.3.3 Current Limit
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN Lower Than 3 V
      2. 7.4.2 Operation With VIN Larger Than 3 V
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

8.2.2.2 Output Capacitor

To ensure the stability of the TPS7B82-Q1, the device requires an output capacitor with a value in the range from 1 μF to 200 μF and with an ESR range between 0.001 Ω and 5 Ω. Select a ceramic capacitor with low ESR to improve the load transient response.