JAJSE23C August   2017  – June 2019 TPS1H000-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なブロック図
      2.      自動再試行モードでの電流制限保護
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 DELAY Pin Configuration
        1. 7.3.2.1 Holding Mode
        2. 7.3.2.2 Latch-Off Mode
        3. 7.3.2.3 Auto-Retry Mode
      3. 7.3.3 Standalone Operation
      4. 7.3.4 Fault Truth Table
      5. 7.3.5 Full Diagnostics
        1. 7.3.5.1 Short-to-GND and Overload Detection
        2. 7.3.5.2 Open-Load Detection
          1. 7.3.5.2.1 Output On
          2. 7.3.5.2.2 Output Off
        3. 7.3.5.3 Short-to-Battery Detection
        4. 7.3.5.4 Thermal Fault Detection
          1. 7.3.5.4.1 Thermal Shutdown
          2. 7.3.5.4.2 Thermal Swing
          3. 7.3.5.4.3 Fault Report Holding
      6. 7.3.6 Full Protections
        1. 7.3.6.1 UVLO Protection
        2. 7.3.6.2 Inductive Load Switching Off Clamp
        3. 7.3.6.3 Loss-of-GND Protection
        4. 7.3.6.4 Loss-of-Power-Supply Protection
        5. 7.3.6.5 Reverse-Current Protection
        6. 7.3.6.6 MCU I/O Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Modes
        1. 7.4.1.1 Normal Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Standby Mode With Diagnostics
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

7.3.2.2 Latch-Off Mode

Latch-off mode is active when the DELAY pin connects to GND through a capacitor. When hitting a current limit, the output current holds at the setting current, but latches off after a preset DELAY time (tdl1+ tdl2). tdl1 is the default delay time, tdl2 is a configurable delay time set by a capacitor. The output stays latched off regardless of whether the current limit is removed. The output recovers only when IN is toggling.

tdl2 can be calculated by Equation 2. The Idl(chg)is the device charging current in latch-off mode, Vdl(ref) is the internal reference voltage in latch off mode, tdl2 is the user-setting delay time, and CDELAY is the capacitor connected on the DELAY pin.

Equation 2. TPS1H000-Q1 Equation-2.gif
TPS1H000-Q1 Latch-Off-1.gifFigure 16. Latch-Off-Mode Connection
TPS1H000-Q1 Latch-Off-2.gifFigure 17. Latch-Off-Mode Example