8.2.2.6 Calculation of ZVS Sensing Network

There are four components in the application circuit to help the depletion MOSFET (Q_S) perform ZVS sensing safely, C_SWS, R_SWS, D_SWS, and R_HVG. Design considerations and selection guidelines for the values of these components are given here.

At the rising edge of the switch node, the fast dV/dt coupling through the drain-to-source capacitance of Q_S (C_OSS(Qs)) generates a charge current flowing into the capacitive loading of the Q_S source pin. The result is a voltage overshoot on both the SWS pin and across the gate-to-source of Q_S (V_GS(Qs)). The SWS pin, with an absolute maximum voltage of 38 V, can handle higher voltage stress than V_GS(Qs). Therefore, a capacitor between the SWS pin and GND (C_SWS) should be selected properly to prevent the voltage overshoot from damaging the Q_S gate. Since C_OSS(Qs) and C_SWS form a voltage divider, the minimum C_SWS (C_SWS(MIN)) can be derived as

where V_{GS_MAX(Qs)} is the de-rated maximum gate-to-source voltage of Q_S, V_HVG is the steady-state voltage level of 11 V, and C_Dsws is the parasitic capacitance of TVS diode (D_SWS) on the SWS pin.

Without resistive damping, both the charge current on the rising edge of V_SW and the discharge current on the falling edge of V_SW are oscillatory with the parasitic inductance within the ZVS sensing network resonating with C_SWS. Therefore, a series resistor (R_SWS) between SWS pin and source-pin of Q_S is used to dampen the high-frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any high-frequency current from interfering with other noise-sensitive signals. R_SWS can be expressed as:

where L_SWS is the lumped parasitic inductance including the packaging of Q_S and PCB traces of Q_S and C_SWS return path.

Based on the above design guide, even though R_SWS and C_SWS may be sufficient to manage the voltage overshoot in normal operation, a low-capacitance TVS diode (D_SWS) is still highly recommended to serve as a safety backup of the ZVS sensing network. A regular Zener diode is not suitable due to its high capacitance and slow clamping response.

Based on the above equations, a general recommendation is that a 50 V C0G-type ceramic capacitor of 22 pF for C_SWS, a chip resistor no higher than 120 Ω for R_SWS, and a TVS diode with the clamp voltage between 18 V to 24 V for D_SWS. Too large of R_SWS or C_SWS introduces a sensing delay between V_SW and SWS pin, so the ZVS control pulls down V_SW earlier than expected before the end of t_Z by unnecessarily extending t_DM. The recommended R_SWS and C_SWS values only introduce a minor 2.6-ns delay, so the ZVS control is not be affected.

Another issue with too large of R_SWS is that an additional voltage drop may be created by the charge current through C_OSS(Qs) during high dV/dt events of V_SW, which becomes another voltage stress onto the gate-to-source voltage of Q_S . For the power stage that can generate very high dV/dt, lowering R_SWS and increasing C_SWS may be necessary to enhance the protection on Q_S. Alternatively, a back-to-back TVS can be added between the gate and source pins of Q_S to provide a direct clamping to the possible over-voltage stress condition. Furthermore, a high-impedance discharge resistor (R_HVG) between the gate and source pins of Q_S helps to discharge the residual voltage on the gate capacitance, and R_HVG around 1 MΩ should be enough to serve the purpose. Note that too small R_HVG can hurt standby power, since it creates a continuous current flowing through Q_S.