JAJSE45C February   2016  – December 2021 SN65DP141

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics, I2C Interface
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC and AC Independent Gain Control
      2. 8.3.2 Two-Wire Serial Interface and Control Logic
      3. 8.3.3 Bus Idle
      4. 8.3.4 Start Data Transfer
      5. 8.3.5 Stop Data Transfer
      6. 8.3.6 Data Transfer
      7. 8.3.7 Acknowledge
    4. 8.4 Device Functional Modes
      1. 8.4.1 TRACE and CABLE Equalization Modes
      2. 8.4.2 Control Modes
      3. 8.4.3 GPIO MODE
      4. 8.4.4 I2C Mode
    5. 8.5 Register Maps
      1. 8.5.1  Register 0x00 (General Device Settings) (offset = 00000000) [reset = 00000000]
      2. 8.5.2  Register 0x01 (Channel Enable) (offset = 00000000) [reset = 00000000]
      3. 8.5.3  Register 0x02 (Channel 0 Control Settings) (offset = 00000000) [reset = 00000000]
      4. 8.5.4  Register 0x03 (Channel 0 Enable Settings) (offset = 00000000) [reset = 00000000]
      5. 8.5.5  Register 0x05 (Channel 1 Control Settings) (offset = 00000000) [reset = 00000000]
      6. 8.5.6  Register 0x06 (Channel 1 Enable Settings) (offset = 00000000) [reset = 00000000]
      7. 8.5.7  Register 0x08 (Channel 2 Control Settings) (offset = 00000000) [reset = 00000000]
      8. 8.5.8  Register 0x09 (Channel 2 Enable Settings) (offset = 00000000) [reset = 00000000]
      9. 8.5.9  Register 0x0B (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
      10. 8.5.10 Register 0x0C (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.4.3 GPIO MODE

Device Pins RX_GAIN, EQ1 and EQ0 determines receiver DC and AC gain as shown in Table 8-1 and Table 8-2.

Table 8-1 EQ Pin Settings
EQ1EQ0EQ Setting
GNDGND000
GNDHiZ000
GNDVCC001
HiZGND010
HiZHiZ011
HiZVCC100
VCCGND101
VCCHiZ110
VCCVCC111
Table 8-2 RX DC and AC GAIN Settings
EQ ConfigurationEQ Gain
EQ SettingRX_GAINEQ_DC_GAIN (dB)EQ_AC_GAIN (dB)
000 - 111LOW–61 - 9
000 - 111HiZ–67 - 17
000 - 111HIGH01 - 9