JAJSE92B November   2017  – April 2018 TPSM84824

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     過渡応答
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Switching Frequency (RT)
      3. 7.3.3  Synchronization (CLK)
      4. 7.3.4  Output On/Off Enable (EN)
      5. 7.3.5  Input Capacitor Selection
      6. 7.3.6  Output Capacitor Selection
      7. 7.3.7  TurboTrans (TT)
        1. 7.3.7.1 Low-ESR Output Capacitors
        2. 7.3.7.2 Transient Response
          1. 7.3.7.2.1 Transient Waveforms (VIN = 12 V)
      8. 7.3.8  Undervoltage Lockout (UVLO)
      9. 7.3.9  Soft Start (SS/TR)
      10. 7.3.10 Sequencing (SS/TR)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Safe Start-up into Pre-Biased Outputs
      13. 7.3.13 Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 Input Capacitors
        5. 8.2.2.5 Output Capacitors
        6. 8.2.2.6 TurboTrans Resistor
        7. 8.2.2.7 Application Waveforms
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 EMI
      1. 10.3.1 EMI Plots
    4. 10.4 Package Specifications
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

9 Power Supply Recommendations

The TPSM84824 is designed to operate from an input voltage supply range between 4.5 V and 17 V. This input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the TPSM84824 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the TPSM84824 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Typically, a 47-µF or 100-μF electrolytic capacitor will suffice.