JAJSE93B March   2016  – November 2017 LM5161

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的な降圧アプリケーション回路
      2.      代表的なFly-Buckアプリケーション回路
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Circuit
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Soft-Start
      5. 7.3.5  Error Transconductance (GM) Amplifier
      6. 7.3.6  On-Time Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  N-Channel Buck Switch and Driver
      9. 7.3.9  Synchronous Rectifier
      10. 7.3.10 Enable / Undervoltage Lockout (EN/UVLO)
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Pulse Width Modulation (FPWM) Mode
      2. 7.4.2 Undervoltage Detector
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM5161 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Resistor Divider Selection
          3. 8.2.1.2.3  Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  Series Ripple Resistor - RESR (FPWM = 1)
          7. 8.2.1.2.7  VCC and Bootstrap Capacitor
          8. 8.2.1.2.8  Input Capacitor Selection
          9. 8.2.1.2.9  Soft-Start Capacitor Selection
          10. 8.2.1.2.10 EN/UVLO Resistor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LM5161 Isolated Fly-Buck (36-V to 72-V Input, 12-V, 12-W Isolated Output)
        1. 8.2.2.1 LM5161 Fly-Buck Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Selection of VOUT and Turns Ratio
          2. 8.2.2.2.2 Secondary Rectifier Diode
          3. 8.2.2.2.3 External Ripple Circuit
          4. 8.2.2.2.4 Output Capacitor (CVISO)
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Ripple Configuration
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C(1)(2) for LM5161. Unless otherwise stated, VIN = 48 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISD Input shutdown current VIN = 48 V, EN/UVLO = 0 V 50 90 µA
IOP Input operating current VIN = 48 V, FB = 3 V, Non-switching 2.3 2.8 mA
VCC SUPPLY
VCC Bias regulator output VIN = 48 V, ICC = 20 mA 6.3 7.3 8.5 V
VCC Bias regulator current limit VIN = 48 V 30 mA
VCC(UV) VCC undervoltage threshold VCC rising 3.98 4.1 V
VCC(HYS) VCC undervoltage hysteresis VCC falling 185 mV
VCC(LDO) VIN - VCC dropout voltage VIN = 4.5 V, ICC = 20 mA 200 340 mV
HIGH-SIDE FET
RDS(ON) High-side on resistance V(BST - SW) = 7 V, ISW = 0.5A 0.58 Ω
BST(UV) Bootstrap gate drive UV V(BST - SW) rising 2.93 3.6 V
BST(HYS) Gate drive UV hysteresis V(BST - SW) falling 200 mV
LOW-SIDE FET
RDS(ON) Low-side on resistance ISW = 0.5 A 0.24 Ω
HIGH-SIDE CURRENT LIMIT
ILIM(HS) High-side current limit threshold 1.3 1.61 1.9 A
TRES Current limit response time ILIM(HS)threshold detect to FET turn-off 100 ns
TOFF Current limit forced off-time FB = 0 V, VIN = 72 V 13 16.5 21 µs
TOFF1 Current limit forced off-time FB = 0.1 V, VIN = 72 V 10 13 17 µs
TOFF2 Current limit forced off-time FB = 1 V, VIN = 72 V 2 2.7 4.1 µs
LOW-SIDE CURRENT LIMIT
ISOURCE(LS) Sourcing current limit 1.3 1.6 1.9 A
ISINK(LS) Sinking current limit 3
DIODE EMULATION
VFPWM(LOW) FPWM input logic low VIN = 48 V 1 V
VFPWM(HIGH) FPWM input logic high VIN = 48 V 3
IZX Zero cross detect current FPWM = 0 (Diode emulation) 22.5 mA
REGULATION COMPARATOR
VREF FB regulation level VIN = 48 V 1.975 2 2.015 V
I(BIAS) FB input bias current VIN = 48 V 100 nA
ERROR CORRECTION AMPLIFIER AND SOFT START
GM Error amp transconductance FB = VREF (±) 10 mV 100 µA/V
IEA(SOURCE) Error amp source current FB = 1 V, SS = 1 V 7.5 10 12.5 µA
IEA(SINK) Error amp sink current FB = 5 V, SS = 2.25 V 7.5 10 12.5
V(SS-FB) VSS - VFB clamp voltage FB = 1.75 V, CSS= 1 nF 135 mV
ISS Soft-start charging current SS = 0.5 V 7.5 10 12.5 µA
ENABLE/UVLO
VUVLO(TH) UVLO threshold EN/UVLO rising 1.195 1.24 1.272 V
IUVLO(HYS) UVLO hysteresis current EN/UVLO = 1.4 V 15 20 25 µA
VSD(TH) Shutdown mode threshold EN/UVLO falling 0.29 0.35 V
VSD(HYS) Shutdown threshold hysteresis EN/UVLO rising 50 mV
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 175 °C
TSD(HYS) Thermal shutdown hysteresis 20 °C
  1. All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
  2. The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.