JAJSE97D June   2017  – May 2019 DAC8740H , DAC8741H

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: DAC8740H
    2.     Pin Functions: DAC8741H
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  HART Modulator
      2. 9.3.2  HART Demodulator
      3. 9.3.3  FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder
      4. 9.3.4  FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder
      5. 9.3.5  Internal Reference
      6. 9.3.6  Clock Configuration
      7. 9.3.7  Reset and Power-Down
      8. 9.3.8  Full-Duplex Mode
      9. 9.3.9  I/O Selection
      10. 9.3.10 Jabber Inhibitor
    4. 9.4 Device Functional Modes
      1. 9.4.1 UART Interfaced HART
      2. 9.4.2 UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      3. 9.4.3 SPI Interfaced HART
      4. 9.4.4 SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      5. 9.4.5 Digital Interface
        1. 9.4.5.1 UART
          1. 9.4.5.1.1 UART Carrier Detect
        2. 9.4.5.2 SPI
          1. 9.4.5.2.1 SPI Cyclic Redundancy Check
          2. 9.4.5.2.2 SPI Interrupt Request
    5. 9.5 Register Maps
      1. 9.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 9. CONTROL Register Field Descriptions
      2. 9.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 10. RESET Register Field Descriptions
      3. 9.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 11. MODEM_STATUS Register Field Descriptions
      4. 9.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 12. MODEM_IRQ_MASK Register Field Descriptions
      5. 9.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 13. MODEM_CONTROL Register Field Descriptions
      6. 9.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 14. FIFO_D2M Register Field Descriptions
      7. 9.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 15. FIFO_M2D Register Field Descriptions
      8. 9.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 16. FIFO_LEVEL_SET Register Field Descriptions
      9. 9.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 17. PAFF_JABBER Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Design Recommendations
      2. 10.1.2 Selecting the Crystal or Resonator
      3. 10.1.3 Included Functions and Filter Selection
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 DAC8740H HART Modem
        2. 10.2.2.2 2-Wire Current Loop
        3. 10.2.2.3 Regulator
        4. 10.2.2.4 DAC
        5. 10.2.2.5 Amplifiers
        6. 10.2.2.6 Diodes
        7. 10.2.2.7 Passives
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.4.5.2.2 SPI Interrupt Request

SPI interfaced devices include an interrupt request, or IRQ, pin to communicate the occurrence of a variety of events to the host controller. The behavior of the IRQ pin is controlled by the CONTROL register and MODEM IRQ MASK register.

The CONTROL register allows the host controller to configure the IRQ pin as level sensitive or edge sensitive via the IRQ LEVEL bit (bit 2). For both level sensitive and edge sensitive modes, the polarity of the IRQ pin can be set via the IRQ POLARITY bit (bit 3) in the CONTROL register.

The MODEM IRQ MASK register allows the controller to decide which events are able to trigger the IRQ pin to toggle. If a logic 0 is written to the respective bit, that event is allowed to toggle the IRQ pin. If a logic 1 is written to the respective bit, the event is masked from the IRQ pin.

When an event occurs the IRQ pin signal, in the case of level-sensitive configurations, is latched and the IRQ pin voltage stays at logic high until the status has been reset, or cleared, by reading the contents of the MODEM_STATUS register. In the case of edge-sensitive configurations a pulse is generated any time a new event is detected.