JAJSEC1C
November 2019 – July 2020
ADS8686S
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Timing Diagrams: Universal
6.9
Timing Diagrams: Parallel Data Read
6.10
Timing Diagrams: Serial Data Read
6.11
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Analog Inputs
7.3.2
Analog Input Impedance
7.3.3
Input Clamp Protection Circuit
7.3.4
Programmable Gain Amplifier (PGA)
7.3.5
Second-Order, Programmable, Low-Pass Filter (LPF)
7.3.6
ADC Driver
7.3.7
Multiplexer
7.3.8
Digital Filter and Noise
7.3.9
Reference
7.3.9.1
Internal Reference
7.3.9.2
External Reference
7.3.9.3
Supplying One VREF to Multiple Devices
7.3.10
ADC Transfer Function
7.4
Device Functional Modes
7.4.1
Device Interface: Pin Description
7.4.1.1
REFSEL (Input)
7.4.1.2
RESET (Input)
7.4.1.3
SEQEN (Input)
7.4.1.4
HW_RANGESEL[1:0] (Input)
7.4.1.5
SER/BYTE/PAR (Input)
7.4.1.6
DB[3:0] (Input/Output)
7.4.1.7
DB4/SER1W (Input/Output)
7.4.1.8
DB5/CRCEN (Input/Output)
7.4.1.9
DB[7:6] (Input/Output)
7.4.1.10
DB8 (Input/Output)
7.4.1.11
DB9/BYTESEL (Input/Output)
7.4.1.12
DB10/SDI (Input/Output)
7.4.1.13
DB11/SDOB (Input/Output)
7.4.1.14
DB12/SDOA (Input/Output)
7.4.1.15
DB13/OS0 (Input/Output)
7.4.1.16
DB14/OS1 (Input/Output)
7.4.1.17
DB15/OS2 (Input/Output)
7.4.1.18
WR/BURST (Input)
7.4.1.19
SCLK/RD (Input)
7.4.1.20
CS (Input)
7.4.1.21
CHSEL[2:0] (Input)
7.4.1.22
BUSY (Output)
7.4.1.23
CONVST (Input)
7.4.2
Device Modes of Operation
7.4.2.1
Shutdown Mode
7.4.2.2
Operation Mode
7.4.2.2.1
Hardware Mode
7.4.2.2.2
Software Mode
7.4.2.3
Reset Functionality
7.4.2.4
Channel Selection
7.4.2.4.1
Hardware Mode Channel Selection
7.4.2.4.2
Software Mode Channel Selection
7.4.2.5
Sequencer
7.4.2.5.1
Hardware Mode Sequencer
7.4.2.5.2
Software Mode Sequencer
7.4.2.6
Burst Sequencer
7.4.2.6.1
Hardware Mode Burst Sequencer
7.4.2.6.2
Software Mode Burst Sequencer
7.4.2.7
Diagnostics
7.4.2.7.1
Analog Diagnosis
7.4.2.7.2
Interface Diagnosis: SELF TEST and CRC
7.5
Programming
7.5.1
Parallel Interface
7.5.1.1
Reading Conversion Results
7.5.1.2
Writing Register Data
7.5.1.3
Reading Register Data
7.5.2
Parallel Byte Interface
7.5.2.1
Reading Conversion Results
7.5.2.2
Writing Register Data
7.5.2.3
Reading Register Data
7.5.3
Serial Interface
7.5.3.1
Reading Conversion Results
7.5.3.2
Writing Register Data
7.5.3.3
Reading Register Data
7.6
Register Maps
7.6.1
Page1 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
8x2 Channel Data Acquisition System (DAQ) for Power Automation
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curve
8.2.2
Input Protection for Electrical Overstress
9
Power Supply Recommendations
9.1
Power Supplies
10
Layout
10.1
Layout Guidelines
10.2
Layout Examples
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
サポート・リソース
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
1
特長
アナログ・フロントエンド内蔵の 16 チャネル、16 ビット ADC
デュアル同時サンプリング:8x2 チャネル
電源電圧:
アナログ:5V
デジタル:1.8V~5V
1MΩ 固定入力インピーダンスのフロントエンド
入力範囲を別々にプログラム可能、20% のオーバーレンジ付き
プログラム可能なローパス・フィルタ
15kHz、39kHz、376kHz
優れた DC および AC 性能
オンチップ基準電圧とリファレンス・バッファ
優れた高温特性
8kV ESD の過電圧入力クランプ
オプションの巡回冗長性検査 (CRC) エラー・チェック
オンチップの自己診断機能
温度範囲:–40℃~+125℃