JAJSEC1C November   2019  – July 2020 ADS8686S

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams: Universal
    9. 6.9  Timing Diagrams: Parallel Data Read
    10. 6.10 Timing Diagrams: Serial Data Read
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Programmable, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer
      8. 7.3.8  Digital Filter and Noise
      9. 7.3.9  Reference
        1. 7.3.9.1 Internal Reference
        2. 7.3.9.2 External Reference
        3. 7.3.9.3 Supplying One VREF to Multiple Devices
      10. 7.3.10 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RESET (Input)
        3. 7.4.1.3  SEQEN (Input)
        4. 7.4.1.4  HW_RANGESEL[1:0] (Input)
        5. 7.4.1.5  SER/BYTE/PAR (Input)
        6. 7.4.1.6  DB[3:0] (Input/Output)
        7. 7.4.1.7  DB4/SER1W (Input/Output)
        8. 7.4.1.8  DB5/CRCEN (Input/Output)
        9. 7.4.1.9  DB[7:6] (Input/Output)
        10. 7.4.1.10 DB8 (Input/Output)
        11. 7.4.1.11 DB9/BYTESEL (Input/Output)
        12. 7.4.1.12 DB10/SDI (Input/Output)
        13. 7.4.1.13 DB11/SDOB (Input/Output)
        14. 7.4.1.14 DB12/SDOA (Input/Output)
        15. 7.4.1.15 DB13/OS0 (Input/Output)
        16. 7.4.1.16 DB14/OS1 (Input/Output)
        17. 7.4.1.17 DB15/OS2 (Input/Output)
        18. 7.4.1.18 WR/BURST (Input)
        19. 7.4.1.19 SCLK/RD (Input)
        20. 7.4.1.20 CS (Input)
        21. 7.4.1.21 CHSEL[2:0] (Input)
        22. 7.4.1.22 BUSY (Output)
        23. 7.4.1.23 CONVST (Input)
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Shutdown Mode
        2. 7.4.2.2 Operation Mode
          1. 7.4.2.2.1 Hardware Mode
          2. 7.4.2.2.2 Software Mode
        3. 7.4.2.3 Reset Functionality
        4. 7.4.2.4 Channel Selection
          1. 7.4.2.4.1 Hardware Mode Channel Selection
          2. 7.4.2.4.2 Software Mode Channel Selection
        5. 7.4.2.5 Sequencer
          1. 7.4.2.5.1 Hardware Mode Sequencer
          2. 7.4.2.5.2 Software Mode Sequencer
        6. 7.4.2.6 Burst Sequencer
          1. 7.4.2.6.1 Hardware Mode Burst Sequencer
          2. 7.4.2.6.2 Software Mode Burst Sequencer
        7. 7.4.2.7 Diagnostics
          1. 7.4.2.7.1 Analog Diagnosis
          2. 7.4.2.7.2 Interface Diagnosis: SELF TEST and CRC
    5. 7.5 Programming
      1. 7.5.1 Parallel Interface
        1. 7.5.1.1 Reading Conversion Results
        2. 7.5.1.2 Writing Register Data
        3. 7.5.1.3 Reading Register Data
      2. 7.5.2 Parallel Byte Interface
        1. 7.5.2.1 Reading Conversion Results
        2. 7.5.2.2 Writing Register Data
        3. 7.5.2.3 Reading Register Data
      3. 7.5.3 Serial Interface
        1. 7.5.3.1 Reading Conversion Results
        2. 7.5.3.2 Writing Register Data
        3. 7.5.3.3 Reading Register Data
    6. 7.6 Register Maps
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 8x2 Channel Data Acquisition System (DAQ) for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Input Protection for Electrical Overstress
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

5 Pin Configuration and Functions

GUID-EFD196FA-41AC-437A-B66D-62D8EA0134B0-low.gifFigure 5-1 PM Package: PZA,80-Pin LQFP(Top View)
Table 5-1 Pin Functions
NAME NO. TYPE(1) DESCRIPTION
AGND 5, 16, 29, 72 P Analog supply ground pins
AIN_0AGND 27 AI Analog input channel 0A: negative input
AIN_0A 28 AI Analog input channel 0A: positive input
AIN_0BGND 74 AI Analog input channel 0B: negative input
AIN_0B 73 AI Analog input channel 0B: positive input
AIN_1AGND 25 AI Analog input channel 1A: negative input
AIN_1A 26 AI Analog input channel 1A: positive input
AIN_1BGND 76 AI Analog input channel 1B: negative input
AIN_1B 75 AI Analog input channel 1B: positive input
AIN_2AGND 23 AI Analog input channel 2A: negative input
AIN_2A 24 AI Analog input channel 2A: positive input
AIN_2BGND 78 AI Analog input channel 2B: negative input
AIN_2B 77 AI Analog input channel 2B: positive input
AIN_3AGND 21 AI Analog input channel 3A: negative input
AIN_3A 22 AI Analog input channel 3A: positive input
AIN_3BGND 80 AI Analog input channel 3B: negative input
AIN_3B 79 AI Analog input channel 3B: positive input
AIN_4AGND 20 AI Analog input channel 4A: negative input
AIN_4A 19 AI Analog input channel 4A: positive input
AIN_4BGND 1 AI Analog input channel 4B: negative input
AIN_4B 2 AI Analog input channel 4B: positive input
AIN_5AGND 18 AI Analog input channel 5A: negative input
AIN_5A 17 AI Analog input channel 5A: positive input
AIN_5BGND 3 AI Analog input channel 5B: negative input
AIN_5B 4 AI Analog input channel 5B: positive input
AIN_6AGND 13 AI Analog input channel 6A: negative input
AIN_6A 14 AI Analog input channel 6A: positive input
AIN_6BGND 8 AI Analog input channel 6B: negative input
AIN_6B 7 AI Analog input channel 6B: positive input
AIN_7AGND 11 AI Analog input channel 7A: negative input
AIN_7A 12 AI Analog input channel 7A: positive input
AIN_7BGND 10 AI Analog input channel 7B: negative input
AIN_7B 9 AI Analog input channel 7B: positive input
AVDD 6, 15, 30, 71 P Analog supply pins. Decouple these pins to the closest AGND pins.
See the Power Supply Recommendations section.
BUSY 67 DO Logic output indicating an ongoing conversion; see the BUSY (Output) section.
CHSEL0 64 DI Logic input pin to select the channel or program the hardware mode sequencer; see the CHSEL[2:0] (Input) section.
CHSEL1 65 DI Logic input pin to select the channel or program the hardware mode sequencer; see the CHSEL[2:0] (Input) section.
CHSEL2 66 DI Logic input pin to select the channel or program the hardware mode sequencer; see the CHSEL[2:0] (Input) section.
CONVST 68 DI Logic input to control the conversion start input for channel group A and channel group B; see the CONVST (Input) section.
CS 63 DI Active low logic input chip select; see the CS (Input) section.
DB0 41 DIO This pin is the data input/output DB0 (LSB) in parallel and parallel byte interface modes.
In serial mode, this pin must be connected to DGND.
See the DB[3:0] (Input/Output) section.
DB1 42 DIO This pin is the data input/output DB1 in parallel and parallel byte interface modes.
In serial mode, this pin must be connected to DGND.
See the DB[3:0] (Input/Output) section.
DB2 43 DIO This pin is the data input/output DB2 in parallel and parallel byte interface modes.
In serial mode, this pin must be connected to DGND.
See the DB[3:0] (Input/Output) section.
DB3 44 DIO This pin is the data input/output DB3 in parallel and parallel byte interface modes.
In serial mode, this pin must be connected to DGND.
See the DB[3:0] (Input/Output) section.
DB4/ SER1W 45 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB4 in parallel and parallel byte interface modes.
This pin is the logic input pin in serial mode to configure data capture using both SDOA and SDOB or just SDOA. The signal state is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured.
See the DB4/SER1W (Input/Output) section.
DB5/CRCEN 46 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB5 in parallel and parallel byte interface modes.
This pin is the logic input pin in hardware serial mode to enable the cyclic redundancy check (CRC) word. The signal is latched on the release of a full reset, and requires an additional full RESET to be reconfigured.
In software mode, this pin must be connected to DGND.
See the DB5/CRCEN (Input/Output) section.
DB6 47 DIO This pin is the data input/output DB6 in parallel and parallel byte interface modes.
See the DB[7:6] (Input/Output) section.
DB7 48 DIO This pin is the data input/output DB7 in parallel and parallel byte interface modes.
See the DB[7:6] (Input/Output) section.
DB8 53 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB8 in parallel interface mode.
In serial mode, this pin must be connected to DGND.
See the DB8 (Input/Output) section.
DB9/BYTESEL 54 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB9 in parallel interface mode.
This pin is the logic input pin that enables the parallel byte interface. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured.
See the DB9/BYTESEL (Input/Output) section.
DB10/SDI 55 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB10 in parallel interface mode.
This pin is the serial data input that programs the device in software serial mode.
Tie this pin to DGND for parallel byte interface mode.
See the DB10/SDI (Input/Output) section.
DB11/SDOB 56 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB11 in parallel interface mode.
This pin is the serial data output port B in serial interface mode if enabled by the DB4/ SER1W pin at full RESET.
Tie this pin to DGND when in parallel byte interface mode.
See the DB11/SDOB (Input/Output) section.
DB12/SDOA 57 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB12 in parallel interface mode.
This pin is the serial data output port A in serial interface mode.
Tie this pin to DGND when in parallel byte interface mode.
See the DB12/SDOA (Input/Output) section.
DB13/OS0 58 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB13 in parallel interface mode.
This pin is the logic input pin for the oversampling rate (OSR) setting. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured.
See the DB13/OS0 (Input/Output) section.
DB14/OS1 59 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB14 in parallel interface mode.
This pin is the logic input pin for the OSR setting. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured.
See the DB14/OS1 (Input/Output) section.
DB15/OS2 60 DIO This pin is a multifunctional logic input/output pin.
This pin is the data input/output DB15 in parallel interface mode.
This pin is the logic input pin for the OSR setting. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured.
See the DB15/OS2 (Input/Output) section.
DGND 50 P Digital ground
DVDD 49 P Digital supply pin. Decouple with DGND on pin 50 with a minimum 0.1-µF capacitor.
HW_RNGSEL1, HW_RNGSEL0 38, 39 DI Hardware and software mode selection inputs. Hardware and software mode selection is latched at full reset. In hardware mode, these pins select the input range and are not latched. In software mode, these pins are latched and ignored until the next RESET event.
HW_RNGSELx = 00: software mode; the ADS8686S is configured via the software registers.
HW_RNGSELx = 01: hardware mode; the analog input range is ±2.5 V.
HW_RNGSELx = 10: hardware mode; the analog input range is ±5 V.
HW_RNGSELx = 11: hardware mode; the analog input range is ±10 V.
See the HW_RANGESEL[1:0] (Input) section.
REFCAP 31 AO Reference amplifier output pin. This pin must be decoupled to REFGND using a low equivalent series resistance (ESR), 10-µF ceramic capacitor. Place this capacitor as close to the REFCAP pin as possible.
Do not drive any external load from this pin.
REFGND 32 P Reference GND. Connect this pin to the AGND plane with the shortest trace possible.
REFIO 33 AIO This pin acts as an internal reference output when REFSEL is high.
This pin functions as an input pin for the external reference when REFSEL is low.
Decouple this pin with REFIO_GND on pin 34 using a 0.1-µF capacitor.
REFIO_GND 34 P REFIO ground. Connect this pin to the AGND plane with the shortest trace possible.
REFSEL 35 DI Active high logic input to enable the internal reference.
See the REFSEL (Input) section.
REGCAP 70 P Voltage output from the internal analog regulator. Decouple this output pin separately to REGGND using a 10-µF capacitor. Place the capacitor close to the REGCAP pin.
REGCAPD 52 P Voltage output from the internal digital regulator. Decouple this output pin separately to REGGNDD using a 10-µF capacitor. Place the capacitor close to the REGCAPD pin.
REGGND 69 P Internal analog regulator GND. Connect this pin to the AGND plane with the shortest trace possible.
REGGNDD 51 P Internal digital regulator GND. Connect this pin to the DGND plane with the shortest trace possible.
RESET 36 DI Active low logic input to reset the device digital logic. The duration of the RESET pulse decides the partial or full RESET of the device.
See the RESET (Input) section.
SCLK/ RD 62 DI This pin is a multifunctional logic input pin.
This pin is the logic input pin for the Serial Clock in serial interface mode.
This pin is the logic input pin in parallel and parallel byte interface modes. When both CS and RD are logic low in parallel and parallel byte modes, the output bus is enabled.
See the SCLK/RD (Input) section.
SEQEN 37 DI Active high logic input to enable the channel sequencer in hardware mode. The state is latched with a device full RESET.
Tie this pin to DGND in software mode.
See the SEQEN (Input) section.
SER/BYTE/ PAR 40 DI Logic input to select between serial, parallel byte, or parallel interface mode.
Tie this pin to logic high and DB9/BYTESEL to logic low to select the serial interface mode.
Tie this pin to logic high and DB9/BYTESEL to logic high to select the parallel BYTE interface mode.
Tie this pin to logic low to select the parallel interface mode.
The signal state is latched at full RESET, and requires an additional full RESET to be reconfigured.
See the SER/BYTE/PAR (Input) section.
WR/BURST 61 DI This pin is a multifunctional logic input pin (see the WR/BURST (Input) section).
WR is the logic input pin to write the register configuration in software parallel and parallel byte interface modes.
BURST is the logic input pin to enable burst mode operation in the hardware mode of operation. The signal is latched on the release of a full RESET, and requires an additional full RESET to be reconfigured; see the Burst Sequencer section.
Tie this pin to DGND when in software serial mode.
(1) AI = analog input, AO = analog output, AIO = analog input/output, DI = digital input, DO = digital output, DIO = digital input/output,
P = power supply.