11.1 Layout Guidelines

Figure 28 and Figure 29 follow proper layout guidelines and should be used as a guide for laying out the LP8556 circuit.

The LP8556 inductive boost converter has a high switched voltage at the SW pin, and a step current through the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference into nearby nodes due to electric field coupling (I = C × dV/dt). The large step current through the diode and the output capacitor can cause a large voltage spike at the SW and VBOOST pins due to parasitic inductance in the step current conducting path (V = L × di/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise.

The following list details the main (layout sensitive) areas of the device inductive boost converter in order of decreasing importance:

1. Boost Output Capacitor Placement
   • Because the output capacitor is in the path of the inductor current discharge path, there is a high-current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series path from the diodes cathode, through COUT, and back into the LP8556 GND pin contributes to voltage spikes (VSPIKE = LP_ × dI/dt) at SW and OUT. These spikes can potentially over-voltage the SW and VBOOST pins, or feed through to GND. To avoid this, COUT+ must be connected as close to the cathode of the Schottky diode as possible, and COUT− must be connected as close to the LP8556 GND bumps as possible. The best placement for COUT is on the same layer as the LP8556 to avoid any vias that can add excessive series inductance.
2. Schottky Diode Placement
   • In the device boost circuit the Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode has a high-current step from 0 to IPEAK each time the switch turns off and the diode turns on. Any inductance in series with the diode causes a voltage spike (VSPIKE = LP_ × dI/dt) at SW and OUT. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor, into GND. Connecting the anode of the diode as close to the SW pin as possible, and connecting the cathode of the diode as close to COUT+ as possible reduces the inductance (LP_) and minimize these voltage spikes.
3. Boost Input/VDD Capacitor Placement
   • The LP8556 input capacitor filters the inductor current ripple and the internal MOSFET driver currents. The inductor current ripple can add input voltage ripple due to any series resistance in the input power path. The MOSFET driver currents can add voltage spikes on the input due to the inductance in series with the VIN/VDD and the input capacitor. Close placement of the input capacitor to the VDD pin and to the GND pin is critical because any series inductance between VIN/VDD and CIN+ or CIN– and GND can create voltage spikes that could appear on the VIN/VDD supply line and GND.
   • Close placement of the input capacitor at the input side of the inductor is also critical. The source impedance (inductance and resistance) from the input supply, along with the input capacitor of the LP8556, forms a series RLC circuit. If the output resistance from the source is low enough, the circuit is underdamped and will have a resonant frequency (typically the case).
   • Depending on the size of LS, the resonant frequency could occur below, close to, or above the switching frequency of the LP8556. This can cause the supply current ripple to be:
     • Approximately equal to the inductor current ripple when the resonant frequency occurs well above the LP8556 switching frequency.
     • Greater than the inductor current ripple when the resonant frequency occurs near the switching frequency.
     • Less than the inductor current ripple when the resonant frequency occurs well below the switching frequency.