JAJSEG5A January   2018  – October 2018 ADS112U04

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      Kタイプ熱電対温度の測定
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 UART Timing Requirements
    7. 7.7 UART Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multiplexer
      2. 9.3.2  Low-Noise Programmable Gain Stage
        1. 9.3.2.1 PGA Input Voltage Requirements
        2. 9.3.2.2 Bypassing the PGA
      3. 9.3.3  Voltage Reference
      4. 9.3.4  Modulator and Internal Oscillator
      5. 9.3.5  Digital Filter
      6. 9.3.6  Conversion Times
      7. 9.3.7  Excitation Current Sources
      8. 9.3.8  Sensor Detection
      9. 9.3.9  System Monitor
      10. 9.3.10 Temperature Sensor
        1. 9.3.10.1 Converting From Temperature to Digital Codes
          1. 9.3.10.1.1 For Positive Temperatures (For Example, 50°C):
          2. 9.3.10.1.2 For Negative Temperatures (For Example, –25°C):
        2. 9.3.10.2 Converting From Digital Codes to Temperature
      11. 9.3.11 Offset Calibration
      12. 9.3.12 Conversion Data Counter
      13. 9.3.13 Data Integrity
      14. 9.3.14 General-Purpose Digital Inputs/Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up and Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Conversion Modes
        1. 9.4.2.1 Single-Shot Conversion Mode
        2. 9.4.2.2 Continuous Conversion Mode
      3. 9.4.3 Operating Modes
        1. 9.4.3.1 Normal Mode
        2. 9.4.3.2 Turbo Mode
        3. 9.4.3.3 Power-Down Mode
    5. 9.5 Programming
      1. 9.5.1 UART Interface
        1. 9.5.1.1 Receive (RX)
        2. 9.5.1.2 Transmit (TX)
        3. 9.5.1.3 Data Ready (DRDY)
        4. 9.5.1.4 Protocol
        5. 9.5.1.5 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1 RESET (0000 011x)
        2. 9.5.3.2 START/SYNC (0000 100x)
        3. 9.5.3.3 POWERDOWN (0000 001x)
        4. 9.5.3.4 RDATA (0001 xxxx)
        5. 9.5.3.5 RREG (0010 rrrx)
        6. 9.5.3.6 WREG (0100 rrrx dddd dddd)
        7. 9.5.3.7 Command Latching
      4. 9.5.4 Reading Data
        1. 9.5.4.1 Manual Data Read Mode
        2. 9.5.4.2 Automatic Data Read Mode
      5. 9.5.5 Data Integrity
    6. 9.6 Register Map
      1. 9.6.1 Configuration Registers
      2. 9.6.2 Register Descriptions
        1. 9.6.2.1 Configuration Register 0 (address = 00h) [reset = 00h]
          1. Table 18. Configuration Register 0 Field Descriptions
        2. 9.6.2.2 Configuration Register 1 (address = 01h) [reset = 00h]
          1. Table 19. Configuration Register 1 Field Descriptions
        3. 9.6.2.3 Configuration Register 2 (address = 02h) [reset = 00h]
          1. Table 21. Configuration Register 2 Field Descriptions
        4. 9.6.2.4 Configuration Register 3 (address = 03h) [reset = 00h]
          1. Table 22. Configuration Register 3 Field Descriptions
        5. 9.6.2.5 Configuration Register 4 (address = 04h) [reset = 00h]
          1. Table 23. Configuration Register 4 Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing Proper Limits on the Absolute Input Voltage
      5. 10.1.5 Unused Inputs and Outputs
      6. 10.1.6 Pseudo Code Example
    2. 10.2 Typical Applications
      1. 10.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Resistive Bridge Measurement
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

8.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 1 to Table 8 summarize the device noise performance. Data are representative of typical noise performance at TA = 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings from a single device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted together. Table 1, Table 3, Table 5, and Table 7 list the input-referred noise in units of μVRMS for the conditions shown. Values in µVPP are shown in parenthesis. Table 2, Table 4, Table 6, and Table 8 list the corresponding data in effective resolution calculated from μVRMS values using Equation 1. Noise-free resolution calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

The input-referred noise (Table 1, Table 3, Table 5, and Table 7) only changes marginally when using an external low-noise reference, such as the REF5020. Use Equation 1 and Equation 2 to calculate effective resolution numbers and noise-free resolution when using a reference voltage other than 2.048 V:

Equation 1. Effective Resolution = ln [2 · VREF / (Gain · VRMS-Noise)] / ln(2)
Equation 2. Noise-Free Resolution = ln [2 · VREF / (Gain · VPP-Noise)] / ln(2)

Table 1. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Enabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
20 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (1.95) 0.98 (0.98) 0.49 (0.49)
45 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (1.95) 0.98 (0.98) 0.49 (0.57)
90 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (2.06) 0.98 (1.20) 0.49 (0.91)
175 62.50 (63.79) 31.25 (37.30) 15.63 (17.00) 7.81 (9.81) 3.91 (5.27) 1.95 (3.32) 0.98 (1.93) 0.49 (1.49)
330 62.50 (107.88) 31.25 (48.95) 15.63 (28.25) 7.81 (14.47) 3.91 (8.06) 1.95 (4.64) 0.98 (2.93) 0.49 (1.91)
600 62.50 (153.77) 31.25 (76.01) 15.63 (38.94) 7.81 (22.30) 3.91 (12.07) 1.95 (6.69) 0.98 (4.49) 0.51 (3.14)
1000 62.50 (228.90) 31.25 (108.90) 15.63 (58.24) 7.81 (31.55) 3.91 (17.41) 1.95 (10.23) 1.04 (6.21) 0.73 (4.69)

Table 2. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Enabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
20 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
45 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.78)
90 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.92) 16 (15.70) 16 (15.10)
175 16 (15.97) 16 (15.74) 16 (15.88) 16 (15.48) 16 (15.57) 16 (15.23) 16 (15.02) 16 (14.39)
330 16 (15.21) 16 (15.35) 16 (15.12) 16 (15.15) 16 (14.96) 16 (14.75) 16 (14.41) 16 (14.03)
600 16 (14.70) 16 (14.72) 16 (14.68) 16 (14.70) 16 (14.37) 16 (14.22) 16 (13.80) 15.83 (13.32)
1000 16 (14.13) 16 (14.20) 16 (14.10) 16 (13.99) 16 (13.99) 16 (13.61) 15.91 (13.33) 15.49 (12.74)

Table 3. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Disabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
20 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
45 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
90 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
175 62.50 (65.71) 31.25 (35.00) 15.63 (16.83)
330 62.50 (106.06) 31.25 (52.59) 15.63 (26.30)
600 62.50 (150.81) 31.25 (79.15) 15.63 (36.87)
1000 62.50 (221.61) 31.25 (111.61) 15.63 (55.07)

Table 4. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Disabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
20 16 (16) 16 (16) 16 (16)
45 16 (16) 16 (16) 16 (16)
90 16 (16) 16 (16) 16 (16)
175 16 (15.93) 16 (15.84) 16 (15.89)
330 16 (15.24) 16 (15.25) 16 (15.25)
600 16 (14.73) 16 (14.66) 16 (14.76)
1000 16 (14.17) 16 (14.16) 16 (14.18)

Table 5. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Enabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
40 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (1.95) 0.98 (0.98) 0.49 (0.51)
90 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (3.91) 1.95 (1.95) 0.98 (0.98) 0.49 (0.76)
180 62.50 (62.50) 31.25 (31.25) 15.63 (15.63) 7.81 (7.81) 3.91 (4.11) 1.95 (2.49) 0.98 (1.51) 0.49 (1.05)
350 62.50 (71.04) 31.25 (37.00) 15.63 (19.17) 7.81 (10.76) 3.91 (5.91) 1.95 (3.54) 0.98 (2.13) 0.49 (1.64)
660 62.50 (105.64) 31.25 (54.97) 15.63 (27.74) 7.81 (16.98) 3.91 (8.45) 1.95 (5.07) 0.98 (3.32) 0.49 (2.38)
1200 62.50 (153.74) 31.25 (78.75) 15.63 (39.68) 7.81 (23.84) 3.91 (13.19) 1.95 (7.46) 0.98 (5.17) 0.58 (3.50)
2000 62.50 (226.39) 31.25 (112.98) 15.63 (59.37) 7.81 (32.97) 3.91 (18.73) 1.95 (11.12) 1.12 (7.06) 0.83 (5.41)

Table 6. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Enabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
40 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.94)
90 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.36)
180 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.93) 16 (15.65) 16 (15.37) 16 (14.90)
350 16 (15.82) 16 (15.76) 16 (15.71) 16 (15.55) 16 (15.40) 16 (15.14) 16 (14.87) 16 (14.25)
660 16 (15.24) 16 (15.19) 16 (15.17) 16 (14.88) 16 (14.89) 16 (14.62) 16 (14.23) 16 (13.71)
1200 16 (14.70) 16 (14.67) 16 (14.66) 16 (14.39) 16 (14.24) 16 (14.07) 16 (13.60) 15.75 (13.16)
2000 16 (14.14) 16 (14.15) 16 (14.07) 16 (13.92) 16 (13.74) 16 (13.49) 15.80 (13.15) 15.23 (12.53)

Table 7. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Disabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
40 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
90 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
180 62.50 (62.50) 31.25 (31.25) 15.63 (15.63)
350 62.50 (72.79) 31.25 (33.34) 15.63 (18.31)
660 62.50 (103.97) 31.25 (51.15) 15.63 (24.69)
1200 62.50 (149.07) 31.25 (76.35) 15.63 (37.48)
2000 62.50 (224.19) 31.25 (113.98) 15.63 (56.87)

Table 8. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Disabled, and Internal VREF = 2.048 V

DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
40 16 (16) 16 (16) 16 (16)
90 16 (16) 16 (16) 16 (16)
180 16 (16) 16 (16) 16 (16)
350 16 (15.78) 16 (15.91) 16 (15.77)
660 16 (15.27) 16 (15.29) 16 (15.34)
1200 16 (14.75) 16 (14.71) 16 (14.74)
2000 16 (14.16) 16 (14.13) 16 (14.14)