JAJSEM0 データシート

JAJSEM0D February 2018 – April 2024 TUSB1044

PRODUCTION DATA

5.7 Timing Requirements

		MIN	MAX	UNIT
I2C Timing
f_SCL	I2C clock frequency		1	MHz
t_BUF	Bus free time between START and STOP conditions	0.5		µs
t_HDSTA	Hold time after repeated START condition. After this period, the first clock pulse is generated	0.26		µs
t_LOW	Low period of the I2C clock	0.5		µs
t_HIGH	High period of the I2C clock	0.26		µs
t_SUSTA	Setup time for a repeated START condition	0.26		µs
t_HDDAT	Data hold time	0		µs
t_SUDAT	Data setup time	50		ns
t_R	Rise time of both SDA and SCL signals		120	ns
t_F	Fall time of both SDA and SCL signals	20 × (VI2C/5.5 V)	120	ns
t_SUSTO	Setup time for STOP condition	0.26		µs
C_BUS	Capacitive load for each bus line		100	pF
HPDIN and CTL1
t_{CTL1_DEBOUNCE}	CTL1 and HPDIN debounce time when transitioning from H to L. DP lanes will be disabled if low is greater than min value.	2.5		ms
USB3.1 and DisplayPort mode transition requirement GPIO mode
t_{GP_USB_4DP}	Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa. Refer to Figure 5-2	4		µs
Power-on timings
t_{d_pg}	V_CC(MIN) to Internal power good asserted high. Refer to Figure 5-8		500	µs
t_{cfg_su}	CFG pins setup. Refer to Figure 5-8	350		µs
t_{cfg_hd}	CFG pin hold. Refer to Figure 5-8	10		µs
t_{ctl_db}	CTL[1:0] and FLIP pin debounce. Refer to Figure 5-8		16	ms
t_{VCC_RAMP}	VCC supply ramp requirement. Refer to Figure 5-8	0.1	100	ms

Figure 5-1 I2C Timing Diagram Definitions

Figure 5-2 USB3.1 to 4-Lane DisplayPort in GPIO Mode

Figure 5-3 Propagation Delay

Figure 5-4 Electrical Idle Mode Exit and Entry Delay

Figure 5-5 Output Rise and Fall Times

Figure 5-6 AUX to SBU Switch ON Timing Diagram

Figure 5-7 AUX to SBU Switch OFF Timing Diagram

Figure 5-8 Power-Up Timing Diagram