JAJSEM0D February   2018  – April 2024 TUSB1044

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.1
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Custom Alternate Mode
      5. 6.4.5 Linear EQ Configuration
      6. 6.4.6 Adjustable VOD Linear Range and DC Gain
      7. 6.4.7 USB3.1 Modes
    5. 6.5 Programming
      1. 6.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
      2. 6.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
      3. 6.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
    6. 6.6 Register Maps
      1. 6.6.1 TUSB1044 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 System Examples
      1. 7.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 7.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 7.3.3 DisplayPort Only
      4. 7.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 7.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 7.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 7.3.7 USB3.1 and 4 Lane of Custom Alt Mode
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Power
PUSB-ACTIVEAverage power when configured for USB 3.1 only mode.Link in U0 with GEN2 data transmission;  EQ control pins = NC; K28.5 pattern at 10 Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p; CTL1 = L; CTL0 = H297mW
PUSB-DP-ACTIVEAverage power when configured for USB 3.1 and 2 lane DP.Link in U0 with GEN2 data transmission and DP active;  EQ control pins = NC; K28.5 pattern at 10 Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p;  CTL1 = H; CTL0 = H578mW
PCUSTOM-ACTIVEAverage power when configured for USB 3.1 and 2 channel custom alt mode.Link in U0 with GEN2 data transmission and custom alt mode active;  EQ control pins = NC; K28.5 pattern at 10 Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p;  CTL1 = H; CTL0 = H578mW
P4DP-ACTIVEAverage power when configured for Four DP lanesFour active DP lanes;  EQ control pins = NC; K28.5 pattern at 10 Gbps; VID = 1000mVp-p;  VOD Linearity = 900mVp-p;  CTL1 = H; CTL0 = L564mW
PUSB-NCAverage power when configured for USB3.1 only and nothing connected to TXP/N pins.No USB device connected;  CTL1 = L; CTL0 = H2.5mW
PUSB-U2U3Average power when configured for USB3.1 only and link in U2 or U3 state.Link in U2 or U3 state;  CTL1 = L; CTL0 = H2mW
PSHUTDOWNAverage power when device in ShutdownCTL1 = L; CTL0 = L; I2C_EN = 0;0.65mW
4-State CMOS Inputs(UEQ[1:0];DEQ[1:0], CFG[1:0], A[1:0], I2C_EN, VIO_SEL)
IIHHigh-level input currentVCC = 3.6 V; VIN = 3.6 V2080µA
IILLow-level input currentVCC = 3.6 V; VIN = 0 V-160-40µA
4-Level VTHThreshold 0 / RVCC = 3.3 V0.55V
Threshold R/ FloatVCC = 3.3 V1.65V
Threshold Float / 1VCC = 3.3 V2.7V
RPUInternal pull up resistance35kΩ
RPDInternal pull-down resistance95kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, HPDIN, SLP_S0#, SWAP, DIR[1:0]).
VIH-3.3VHigh-level input voltageVCC = 3.3V; VIO_SEL = "0" or "R";23.6V
VIL-3.3VLow-level input voltageVCC = 3.3V; VIO_SEL = "0" or "R";00.8V
VIH-1.8VHigh-level input voltageVCC = 3.3V; VIO_SEL = "F" or "1";1.23.6V
VIL-1.8VLow-level input voltageVCC = 3.3V; VIO_SEL = "F" or "1";00.4V
RPD_CTL1Internal pull-down resistance for CTL1, CTL0, DIR0, DIR1, FLIP, SLP_S0#.  500kΩ
RPD_HPDINInternal pull-down resistance for HPDIN500kΩ
RPD_SWAPInternal pull-down resistance for SWAP.  200kΩ
IIHHigh-level input currentVIN = 3.6 V-2525µA
IILLow-level input currentVIN = GND, VCC = 3.6 V-2525µA
I2C Control Pins SCL, SDA
VIH-3.3VHigh-level input voltage. VCC = 3.3V; VIO_SEL = "0" or "F"; I2C Mode Enabled;23.6V
VIL-3.3VLow-level input voltage.  VCC = 3.3V; VIO_SEL = "0" or "F"; I2C Mode Enabled;00.8V
VIH-1.8VHigh-level input voltage.    VCC = 3.3V; VIO_SEL = "R" or "1"; I2C Mode Enabled;1.23.6V
VIL-1.8VLow-level input voltage.    VCC = 3.3V; VIO_SEL = "R" or "1"; I2C Mode Enabled;00.4V
VOLLow-level output voltageI2C_EN ! = 0; IOL = 3 mA00.4V
IOLLow-level output currentI2C_EN ! = 0; VOL = 0.4 V20mA
II_I2CInput current on SDA pin0.1*VI2C < Input voltage < 3.3 V-1010µA
Ci_I2CInput capacitance0.55pF
USB Gen 2 Differential Receiver (UTX1P/N, UTX2P/N, DRX1P/N, DRX2P/N)
VRX-DIFF-PPInput differential peak-peak voltage swing  dynamic rangeAC-coupled differential peak-to-peak signal measured post CTLE through a reference channel2000mVpp
VRX-DC-CMCommon-mode voltage bias in the receiver (DC)0V
RRX-DIFF-DCDifferential input impedance (DC)Present after a GEN 2 device is detected on TXP/TXN72120Ω
RRX-CM-DCReceiver DC Common Mode impedancePresent after a GEN 2 device is detected on TXP/TXN1830Ω
ZRX-HIGH-IMP-DC-POSCommon-mode input impedance with termination disabled (DC)Present when no GEN 2 device is detected on TXP/TXN. Measured over the range of 0-500 mV with respect to GND.25kΩ
VSIGNAL-DET-DIFF-PPInput Differential peak-to-peak Signal Detect Assert Level10 Gbps PRBS7 pattern; low loss input channel;80mV
VRX-IDLE-DET-DIFF-PPInput Differential peak-to-peak Signal Detect De-assert Level10 Gbps PRBS7 pattern; low loss input channel;60mV
VRX-LFPS-DET-DIFF-PPLow-frequency Periodic Signaling (LFPS) Detect ThresholdBelow the minimum is squelched.100300mV
CRXRX input capacitance to GNDAt 5 GHz0.3pF
RLRX-DIFFDifferential Return Loss50 MHz – 2.5 GHz at 90 Ω-13dB
RLRX-DIFF5 GHz at 90 Ω-12dB
RLRX-CMCommon Mode Return Loss50 MHz – 5 GHz at 90 Ω-10.5dB
EQSSPReceiver equalization at maximum settingUEQ[1:0] and DEQ[1:0]. at 5 GHz.10dB
USB Gen 2 Differential Transmitter (DTX1P/N, DTX2P/N, URX1P/N, URX2P/N)
VTX-DIFF-PPTransmitter dynamic differential voltage swing range.1500mVpp
VTX-RCV-DETECTAmount of voltage change allowed during Receiver DetectionAt 3.3 V600mV
VTX-CM-IDLE-DELTATransmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPSmeasured at the connector side of the AC coupling caps with 50 ohm load-600600mV
VTX-DC-CMCommon-mode voltage bias in the transmitter (DC)1.752.3V
VTX-CM-AC-PP-ACTIVETx AC Common-mode voltage activeRx EQ setting matches input channel loss; Max mismatch from Txp + Txn for both time and amplitude; -40℃ to 85℃;100mVpp
VTX-IDLE-DIFF-AC-PPAC Electrical idle differential peak-to-peak output voltageAt package pins010mV
VTX-IDLE-DIFF-DCDC Electrical idle differential output voltageAt package pins after low-pass filter to remove AC component014mV
RTX-DIFFDifferential impedance of the driver75120Ω
CAC-COUPLINGAC Coupling capacitor75265nF
RTX-CMCommon-mode impedance of the driverMeasured with respect to AC ground over 0-500 mV1830Ω
ITX-SHORTTX short circuit currentTX + /- shorted to GND74mA
RLTX-DIFFDifferential Return Loss50 MHz – 2.5 GHz at 90 Ω-13dB
RLTX-DIFFDifferential Return Loss5 GHz at 90 Ω-10.5dB
RLTX-CMCommon Mode Return Loss50 MHz – 5 GHz at 90 Ω-10dB
AC Characteristics
CrosstalkDifferential Cross Talk between TX and RX signal PairsAt 5 GHz-30dB
GLFLow-frequency voltage gain for 0dB setting.At 100 MHz; 200 mVpp < VID < 2000 mVpp; 0 dB DC Gain;-101dB
CP1 dB-LF-1100Low-frequency 1-dB compression pointAt 100 MHz; 200 mVpp < VID < 2000 mVpp; 1100mVpp linearity setting;1100mVpp
CP1 dB-HF-1100High-frequency 1-dB compression pointAt 5 GHz; 200 mVpp < VID < 2000 mVpp; 1100mVpp linearity setting;1200mVpp
fLFLow-frequency cutoff200 mVpp < VID < 2000 mVpp2250kHz
DJTX output deterministic jitter200 mVpp < VID < 2000 mVpp, PRBS7, 10 Gbps0.07UIpp
DJTX output deterministic jitter200 mVpp < VID < 2000 mVpp, PRBS7, 8.1 Gbps0.07UIpp
TJTX output total jitter200 mVpp < VID < 2000 mVpp, PRBS7, 10 Gbps0.11UIpp
TJTX output total jitter200 mVpp < VID < 2000 mVpp, PRBS7, 8.1 Gbps0.11UIpp
DisplayPort Receiver (UTX1P/N, UTX2P/N, URX1P/N, URX2P/N)
VID_PPPeak-to-peak input differential dynamic voltage range1500V
VICInput Common Mode Voltage0V
CACAC coupling capacitance75265nF
EQDPReceiver EqualizerDPEQ1, DPEQ0 at 4.05 GHz9.5dB
dRData rateUHBR1010.0Gbps
RtiInput Termination resistance80100120Ω
DisplayPort Transmitter (DTX1P/N, DTX2P/N, DRX1P/N, DRX2P/N)
VTX-DIFFPPVOD dynamic range1500mV
AUXP/N and SBU1/2
RONOutput ON resistanceVCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI = 2.7 V to 3.6 V for AUXN512Ω
ΔRONON resistance mismatch within pairVCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI = 2.7 V to 3.6 V for AUXN1.3Ω
RON_FLATON resistance flatness (RON max – RON min) measured at identical VCC and temperatureVCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI = 2.7 V to 3.6 V for AUXN2Ω
VAUXP_DC_CMAUX Channel DC common mode voltage for AUXP and SBU1.VCC = 3.3 V00.4V
VAUXN_DC_CMAUX Channel DC common mode voltage for AUXN and SBU2VCC = 3.3 V2.73.6V