JAJSEM0D February   2018  – April 2024 TUSB1044

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.1
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Custom Alternate Mode
      5. 6.4.5 Linear EQ Configuration
      6. 6.4.6 Adjustable VOD Linear Range and DC Gain
      7. 6.4.7 USB3.1 Modes
    5. 6.5 Programming
      1. 6.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
      2. 6.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
      3. 6.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
    6. 6.6 Register Maps
      1. 6.6.1 TUSB1044 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 System Examples
      1. 7.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 7.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 7.3.3 DisplayPort Only
      4. 7.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 7.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 7.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 7.3.7 USB3.1 and 4 Lane of Custom Alt Mode
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.1 Device Configuration in GPIO mode

The TUSB1044 is in GPIO configuration when I2C_EN = “0” or I2C_EN = "F". The TUSB1044 supports operational combinations with USB and two different Type-C Alternate Modes. One combination includes USB and Alternate Mode DisplayPort, and the other combination includes USB and custom Alternate Mode. For each operational combination the data path directions can be further set using the DIR[1:0] pins or through I2C to enable the device to operate in the source or sink sides. Please refer to Table 6-2 for all the configuration of all the operational modes.

When the device is set to operate in a USB and Alternate Mode DisplayPort the following configurations can be further set: USB3.1 only, 2 DisplayPort lanes + USB3.1, or 4 DisplayPort lanes (no USB3.1). The CTL1 pin controls whether DisplayPort mode is enabled. The combination of CTL1 and CTL0 selects between USB3.1 only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 6-2. The AUXP/N to SBU1/2 mapping is controlled based on Table 6-3..

When the device is set to operate in a USB and custom Alternate Mode, the following configurations can be further set: USB3.1 only, 2 Channels of custom Alternate Mode + USB3.1, or 4 Channels of custom Alternate Mode (no USB3.1). The CTL1 pin controls whether custom Alternate Mode is enabled. The combination of CTL1 and CTL0 selects between USB3.1 only, 2 channels of custom Alternate Mode, or 4 channels of custom Alternate Mode as detailed in Table 6-2. The AUXP/N to SBU1/2 mapping is controlled based on Table 6-3.

Further data path direction control can be achieved using the SWAP pin. When set high, the SWAP pin reverses the data path direction on all the channels and swaps the equalization settings of the upstream and downstream facing input ports. This pin may be found useful in active cable application with TUSB1044 installed on only one end. The SWAP pin can be set based on which cable end is plugged to the source or sink side receptacle

After power-up (VCC from 0 V to 3.3 V), the TUSB1044 will default to USB3.1 mode. The USB PD controller, upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device, must take TUSB1044 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.

Table 6-2 GPIO Configuration Control
DIR1
PIN		DIR0
PIN		CTL1
PIN		CTL0
PIN		FLIP
PIN		TUSB1044 CONFIGURATIONVESA DisplayPort ALT MODE
DFP_D Configuration
USB + DisplayPort Alternate Mode (Source Side)
LLLLLPower Down—
LLLLHPower Down—
LLLHLOne Port USB 3.1 - No Flip—
LLLHHOne Port USB 3.1 – With Flip—
LLHLL4 Lane DP - No FlipC and E
LLHLH4 Lane DP – with FlipC and E
LLHHLOne Port USB 3.1 + 2 Lane DP- No FlipD and F
LLHHHOne Port USB 3.1 + 2 Lane DP– with FlipD and F
USB + DisplayPort Alternate Mode (Sink Side)
LHLLLPower Down–
LHLLHPower Down–
LHLHLOne Port USB 3.1 - No Flip–
LHLHHOne Port USB 3.1 – With Flip–
LHHLL4 Lane DP - No FlipC and E
LHHLH4 Lane DP – With FlipC and E
LHHHLOne Port USB 3.1 + 2 Lane DP- No FlipD and F
LHHHHOne Port USB 3.1 + 2 Lane DP– With FlipD and F
USB + Custom Alternate Mode (Source Side)
HLLLLPower Down–
HLLLHPower Down–
HLLHLOne Port USB 3.1 - No Flip–
HLLHHOne Port USB 3.1 – With Flip–
HLHLL4 Channel Custom Alt Mode - No Flip–
HLHLH4 Channel Custom Alt Mode– With Flip–
HLHHLOne Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip		–
HLHHHOne Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip		–
USB + Custom Alternate Mode (Sink Side)
HHLLLPower Down-
HHLLHPower Down-
HHLHLOne Port USB 3.1 - No Flip-
HHLHHOne Port USB 3.1 – With Flip-
HHHLL4 Channel Custom Alt Mode - No Flip-
HHHLH4 Channel Custom Alt Mode– With Flip-
HHHHLOne Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip		-
HHHHHOne Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip		-
Table 6-3 GPIO AUXP/N to SBU1/2 Mapping
CTL1 pinFLIP pinMapping
HLAUXP -> SBU1
AUXN -> SBU2
HHAUXP -> SBU2
AUXN -> SBU1
L > 2msXOpen

Table 6-4 details the TUSB1044 mux routing. This table is valid for GPIO Mode. This table is also valid for I2C mode if CH_SWAP_SEL = 4'b0000 or 4'b1111.

Table 6-4 INPUT to OUTPUT Mapping
SWAP = LSWAP = H
FromFromToFromFromTo
DIR1
PIN		DIR0
PIN		CTL1
PIN		CTL0
PIN		FLIP
PIN		Rx EQ Control
PINS		Input
PIN		Output
PIN		Rx EQ Control
PINS		Input
PIN		Output
PIN
USB + DisplayPort Alternate Mode (Source Side)
LLLLLNANANANANANA
LLLLHNANANANANANA
LLLHLDEQ[1:0]DRX1PURX1P (SSRXP)DEQ[1:0]URX1P (SSTXP)DRX1P
DEQ[1:0]DRX1NURX1N (SSRXN)DEQ[1:0]URX1N (SSTXN)DRX1N
UEQ[1:0]UTX1P (SSTXP)DTX1PUEQ[1:0]DTX1PUTX1P (SSRXP)
UEQ[1:0]UTX1N (SSTXN)DTX1NUEQ[1:0]DTX1NUTX1N (SSRXN)
LLLHHDEQ[1:0]DRX2PURX2P (SSRXP)DEQ[1:0]URX2P (SSTXP)DRX2P
DEQ[1:0]DRX2NURX2N (SSRXN)DEQ[1:0]URX2N (SSTXN)DRX2N
UEQ[1:0]UTX2P (SSTXP)DTX2PUEQ[1:0]DTX2PUTX2P (SSRXP)
UEQ[1:0]UTX2N (SSTXN)DTX2NUEQ[1:0]DTX2NUTX2N (SSRXN)
LLHLLUEQ[1:0]URX2P (DP0P)DRX2PUEQ[1:0]DRX2PURX2P (DP0P)
UEQ[1:0]URX2N (DP0N)DRX2NUEQ[1:0]DRX2NURX2N (DP0N)
UEQ[1:0]UTX2P (DP1P)DTX2PUEQ[1:0]DTX2PUTX2P (DP1P)
UEQ[1:0]UTX2N (DP1N)DTX2NUEQ[1:0]DTX2NUTX2N (DP1N)
UEQ[1:0]UTX1P (DP2P)DTX1PUEQ[1:0]DTX1PUTX1P (DP2P)
UEQ[1:0]UTX1N (DP2N)DTX1NUEQ[1:0]DTX1NUTX1N (DP2N)
UEQ[1:0]URX1P (DP3P)DRX1PUEQ[1:0]DRX1PURX1P (DP3P)
UEQ[1:0]URX1N (DP3N)DRX1NUEQ[1:0]DRX1NURX1N (DP3N)
LLHLHUEQ[1:0]URX1P (DP0P)DRX1PUEQ[1:0]DRX1PURX1P (DP0P)
UEQ[1:0]URX1N (DP0N)DRX1NUEQ[1:0]DRX1NURX1N (DP0N)
UEQ[1:0]UTX1P (DP1P)DTX1PUEQ[1:0]DTX1PUTX1P (DP1P)
UEQ[1:0]UTX1N (DP1N)DTX1NUEQ[1:0]DTX1NUTX1N (DP1N)
UEQ[1:0]UTX2P (DP2P)DTX2PUEQ[1:0]DTX2PUTX2P (DP2P)
UEQ[1:0]UTX2N (DP2N)DTX2NUEQ[1:0]DTX2NUTX2N (DP2N)
UEQ[1:0]URX2P (DP3P)DRX2PUEQ[1:0]DRX2PURX2P (DP3P)
UEQ[1:0]URX2N (DP3N)DRX2NUEQ[1:0]DRX2NURX2N (DP3N)
LLHHLDEQ[1:0]DRX1PURX1P (SSRXP)DEQ[1:0]URX1P (SSTXP)DRX1P
DEQ[1:0]DRX1NURX1N (SSRXN)DEQ[1:0]URX1N (SSTXN)DRX1N
UEQ[1:0]UTX1P (SSTXP)DTX1PUEQ[1:0]DTX1PUTX1P (SSRXP)
UEQ[1:0]UTX1N (SSTXN)DTX1NUEQ[1:0]DTX1NUTX1N (SSRXN)
UEQ[1:0]URX2P (DP0P)DRX2PUEQ[1:0]DRX2PURX2P (DP0P)
UEQ[1:0]URX2N (DP0N)DRX2NUEQ[1:0]DRX2NURX2N (DP0N)
UEQ[1:0]UTX2P (DP1P)DTX2PUEQ[1:0]DTX2PUTX2P (DP1P)
UEQ[1:0]UTX2N (DP1N)DTX2NUEQ[1:0]DTX2NUTX2N (DP1N)
LLHHHDEQ[1:0]DRX2PURX2P (SSRXP)DEQ[1:0]URX2P (SSTXP)DRX2P
DEQ[1:0]DRX2NURX2N (SSRXN)DEQ[1:0]URX2N (SSTXN)DRX2N
UEQ[1:0]UTX2P (SSTXP)DTX2PUEQ[1:0]DTX2PUTX2P (SSRXP)
UEQ[1:0]UTX2N (SSTXN)DTX2NUEQ[1:0]DTX2NUTX2N (SSRXN)
UEQ[1:0]URX1P (DP0P)DRX1PUEQ[1:0]DRX1PURX1P (DP0P)
UEQ[1:0]URX1N (DP0N)DRX1NUEQ[1:0]DRX1NURX1N (DP0N)
UEQ[1:0]UTX1P (DP1P)DTX1PUEQ[1:0]DTX1PUTX1P (DP1P)
UEQ[1:0]UTX1N (DP1N)DTX1NUEQ[1:0]DTX1NUTX1N (DP1N)
USB + DisplayPort Alternate Mode (Sink Side)
LHLLLNANANANANANA
LHLLHNANANANANANA
LHLHLUEQ[1:0]UTX2PDTX2P (SSRXP)UEQ[1:0]DTX2P (SSTXP)UTX2P
UEQ[1:0]UTX2NDTX2N (SSRXN)UEQ[1:0]DTX2N (SSTXN)UTX2N
DEQ[1:0]DRX2P (SSTXP)URX2PDEQ[1:0]URX2PDRX2P (SSRXP)
DEQ[1:0]DRX2N (SSTXN)URX2NDEQ[1:0]URX2NDRX2N (SSRXN)
LHLHHUEQ[1:0]UTX1PDTX1P (SSRXP)UEQ[1:0]DTX1P (SSTXP)UTX1P
UEQ[1:0]UTX1NDTX1N (SSRXN)UEQ[1:0]DTX1N (SSTXN)UTX1N
DEQ[1:0]DRX1P (SSTXP)URX1PDEQ[1:0]URX1PDRX1P (SSRXP)
DEQ[1:0]DRX1N (SSTXN)URX1NDEQ[1:0]URX1NDRX1N (SSRXN)
LHHLLUEQ[1:0]URX2PDRX2P (DP3P)UEQ[1:0]DRX2P (DP3P)URX2P
UEQ[1:0]URX2NDRX2N (DP3N)UEQ[1:0]DRX2N (DP3N)URX2N
UEQ[1:0]UTX2PDTX2P (DP2P)UEQ[1:0]DTX2P (DP2P)UTX2P
UEQ[1:0]UTX2NDTX2N (DP2N)UEQ[1:0]DTX2N (DP2N)UTX2N
UEQ[1:0]UTX1PDTX1P (DP1P)UEQ[1:0]DTX1P (DP1P)UTX1P
UEQ[1:0]UTX1NDTX1N (DP1N)UEQ[1:0]DTX1N (DP1N)UTX1N
UEQ[1:0]URX1PDRX1P (DP0P)UEQ[1:0]DRX1P (DP0P)URX1P
UEQ[1:0]URX1PDRX1N (DP0P)UEQ[1:0]DRX1N (DP0N)URX1N
LHHLHUEQ[1:0]URX1PDRX1P (DP3P)UEQ[1:0]DRX1P (DP3P)URX1P
UEQ[1:0]URX1NDRX1N (DP3N)UEQ[1:0]DRX1N (DP3N)URX1N
UEQ[1:0]UTX1PDTX1P (DP2P)UEQ[1:0]DTX1P (DP2P)UTX1P
UEQ[1:0]UTX1NDTX1N (DP2N)UEQ[1:0]DTX1N (DP2N)UTX1N
UEQ[1:0]UTX2PDTX2P (DP1P)UEQ[1:0]DTX2P (DP1P)UTX2P
UEQ[1:0]UTX2NDTX2N (DP1N)UEQ[1:0]DTX2N (DP1N)UTX2N
UEQ[1:0]URX2PDRX2P (DP0P)UEQ[1:0]DRX2P (DP0P)URX2P
UEQ[1:0]URX2NDRX2N (DP0N)UEQ[1:0]DRX2N (DP0N)URX2N
LHHHLDEQ[1:0]DRX2P (SSRXP)URX2PDEQ[1:0]URX2PDRX2P (SSRXP)
DEQ[1:0]DRX2N (SSRXN)URX2NDEQ[1:0]URX2NDRX2N (SSRXN)
UEQ[1:0]UTX2PDTX2P (SSTXP)UEQ[1:0]DTX2P (SSTXP)UTX2P
UEQ[1:0]UTX2NDTX2N (SSTXN)UEQ[1:0]DTX2N (SSTXN)UTX2N
UEQ[1:0]URX1PDRX1P (DP0P)UEQ[1:0]DRX1P (DP0P)URX1P
UEQ[1:0]URX1NDRX1N (DP0N)UEQ[1:0]DRX1N (DP0N)URX1N
UEQ[1:0]UTX1PDTX1P (DP1P)UEQ[1:0]DTX1P (DP1P)UTX1P
UEQ[1:0]UTX1NDTX1N (DP1N)UEQ[1:0]DTX1N (DP1N)UTX1N
LHHHHDEQ[1:0]DRX1P (SSRXP)URX1PDEQ[1:0]URX1PDRX1P (SSRXP)
DEQ[1:0]DRX1N (SSRXN)URX1NDEQ[1:0]URX1NDRX1N (SSRXN)
UEQ[1:0]UTX1PDTX1P (SSTXP)UEQ[1:0]DTX1P (SSTXP)UTX1P
UEQ[1:0]UTX1NDTX1N (SSTXN)UEQ[1:0]DTX1N (SSTXN)UTX1N
UEQ[1:0]URX2PDRX2P (DP0P)UEQ[1:0]DRX2P (DP0P)URX2P
UEQ[1:0]URX2NDRX2N (DP0N)UEQ[1:0]DRX2N (DP0N)URX2N
UEQ[1:0]UTX2PDTX2P (DP1P)UEQ[1:0]DTX2P (DP1P)UTX2P
UEQ[1:0]UTX2NDTX2N (DP1N)UEQ[1:0]DTX2N (DP1N)UTX2N
USB + Custom Alternate Mode (Source Side)
HLLLLNANANANANANA
HLLLHNANANANANANA
HLLHLDEQ[1:0]DRX1PURX1P (SSRXP)DEQ[1:0]URX1P (SSTXP)DRX1P
DEQ[1:0]DRX1NURX1N (SSRXN)DEQ[1:0]URX1N (SSTXN)DRX1N
UEQ[1:0]UTX1P (SSTXP)DTX1PUEQ[1:0]DTX1PUTX1P (SSRXP)
UEQ[1:0]UTX1N (SSTXN)DTX1NUEQ[1:0]DTX1NUTX1N (SSRXN)
HLLHHDEQ[1:0]DRX2PURX2P (SSRXP)DEQ[1:0]URX2P (SSTXP)DRX2P
DEQ[1:0]DRX2NURX2N (SSRXN)DEQ[1:0]URX2N (SSTXN)DRX2N
UEQ[1:0]UTX2P (SSTXP)DTX2PUEQ[1:0]DTX2PUTX2P (SSRXP)
UEQ[1:0]UTX2N (SSTXN)DTX2NUEQ[1:0]DTX2NUTX2N (SSRXN)
HLHLLDEQ[1:0]DRX2PURX2P (LN1RXP)DEQ[1:0]URX2P (LN1RXP)DRX2P
DEQ[1:0]DRX2NURX2N (LN1RXN)DEQ[1:0]URX2N (LN1RXN)DRX2N
UEQ[1:0]UTX2P (LN1TXP)DTX2PUEQ[1:0]DTX2PUTX2P (LN1TXP)
UEQ[1:0]UTX2N (LN1TXN)DTX2NUEQ[1:0]DTX2NUTX2N (LN1TXN)
UEQ[1:0]UTX1P (LN0TXP)DTX1PUEQ[1:0]DTX1PUTX1P (LN0TXP)
UEQ[1:0]UTX1N (LN0TXN)DTX1NUEQ[1:0]DTX1NUTX1N (LN0TXN)
DEQ[1:0]DRX1PURX1P (LN0RXP)DEQ[1:0]URX1P (LN0RXP)DRX1P
DEQ[1:0]DRX1NURX1N (LN0RXN)DEQ[1:0]URX1N (LN0RXN)DRX1N
HLHLHDEQ[1:0]DRX1PURX1P (LN1RXP)DEQ[1:0]URX1P (LN1RXP)DRX1P
DEQ[1:0]DRX1NURX1N (LN1RXN)DEQ[1:0]URX1N (LN1RXN)DRX1N
UEQ[1:0]UTX1P (LN1TXP)DTX1PUEQ[1:0]DTX1PUTX1P (LN1TXP)
UEQ[1:0]UTX1N (LN1TXN)DTX1NUEQ[1:0]DTX1NUTX1N (LN1TXN)
UEQ[1:0]UTX2P (LN0TXP)DTX2PUEQ[1:0]DTX2PUTX2P (LN0TXP)
UEQ[1:0]UTX2N (LN0TXN)DTX2NUEQ[1:0]DTX2NUTX2N (LN0TXN)
HLHHLDEQ[1:0]DRX2PURX2P (LN0RXP)DEQ[1:0]URX2P (LN0RXP)DRX2P
DEQ[1:0]DRX2NURX2N (LN0RXN)DEQ[1:0]URX2N (LN0RXN)DRX2N
DEQ[1:0]DRX1PURX1P (SSRXP)DEQ[1:0]URX1P (SSTXP)DRX1P
DEQ[1:0]DRX1NURX1N (SSRXN)DEQ[1:0]URX1N (SSTXN)DRX1N
UEQ[1:0]UTX1P (SSTXP)DTX1PUEQ[1:0]DTX1PUTX1P (SSRXP)
UEQ[1:0]UTX1N (SSTXN)DTX1NUEQ[1:0]DTX1NUTX1N (SSRXN)
UEQ[1:0]UTX2P (LN0TXP)DTX2PUEQ[1:0]DTX2PUTX2P (LN0TXP)
UEQ[1:0]UTX2N (LN0TXN)DTX2NUEQ[1:0]DTX2NUTX2N (LN0TXN)
DEQ[1:0]DRX2PURX2P (LN0RXP)DEQ[1:0]URX2P (LN0RXP)DRX2P
DEQ[1:0]DRX2NURX2N (LN0RXN)DEQ[1:0]URX2N (LN0RXN)DRX2N
HLHHHDEQ[1:0]DRX2PURX2P (SSRXP)DEQ[1:0]URX2P (SSTXP)DRX2P
DEQ[1:0]DRX2NURX2N (SSRXN)DEQ[1:0]URX2N (SSTXN)DRX2N
UEQ[1:0]UTX2P (SSTXP)DTX2PUEQ[1:0]DTX2PUTX2P (SSRXP)
UEQ[1:0]UTX2N (SSTXN)DTX2NUEQ[1:0]DTX2NUTX2N (SSRXN)
UEQ[1:0]UTX1P (LN0TXP)DTX1PUEQ[1:0]DTX1PUTX1P (LN0TXP)
UEQ[1:0]UTX1N (LN0TXN)DTX1NUEQ[1:0]DTX1NUTX1N (LN0TXN)
DEQ[1:0]DRX1PURX1P (LN0RXP)DEQ[1:0]URX1P (LN0RXP)DRX1P
DEQ[1:0]DRX1NURX1N (LN0RXN)DEQ[1:0]URX1N (LN0RXN)DRX1N
USB + Custom Alternate Mode (Sink Side)
HHLLLNANANANANANA
HHLLHNANANANANANA
HHLHLUEQ[1:0]UTX2PDTX2P (SSRXP)UEQ[1:0]DTX2P (SSTXP)UTX2P
UEQ[1:0]UTX2NDTX2N (SSRXN)UEQ[1:0]DTX2N (SSTXN)UTX2N
DEQ[1:0]DRX2P (SSTXP)URX2PDEQ[1:0]URX2PDRX2P (SSRXP)
DEQ[1:0]DRX2N (SSTXN)URX2NDEQ[1:0]URX2NDRX2N (SSRXN)
HHLHHUEQ[1:0]UTX1PDTX1P (SSRXP)UEQ[1:0]DTX1P (SSTXP)UTX1P
UEQ[1:0]UTX1NDTX1N (SSRXN)UEQ[1:0]DTX1N (SSTXN)UTX1N
DEQ[1:0]DRX1P (SSTXP)URX1PDEQ[1:0]URX1PDRX1P (SSRXP)
DEQ[1:0]DRX1N (SSTXN)URX1NDEQ[1:0]URX1NDRX1N (SSRXN)
HHHLLDEQ[1:0]DRX2PURX2P (LN1TXP)DEQ[1:0]URX2P (LN1TXP)DRX2P
DEQ[1:0]DRX2NURX2N (LN1TXN)DEQ[1:0]URX2N (LN1TXN)DRX2N
UEQ[1:0]UTX2P (LN1RXP)DTX2PUEQ[1:0]DTX2PUTX2P (LN1RXP)
UEQ[1:0]UTX2N (LN1RXN)DTX2NUEQ[1:0]DTX2NUTX2N (LN1RXN)
UEQ[1:0]UTX1P (LN0RXP)DTX1PUEQ[1:0]DTX1PUTX1P (LN0RXP)
UEQ[1:0]UTX1N (LN0RXN)DTX1NUEQ[1:0]DTX1NUTX1N (LN0RXN)
DEQ[1:0]DRX1PURX1P (LN0RXP)DEQ[1:0]URX1P (LN0RXP)DRX1P
DEQ[1:0]DRX1NURX1N (LN0RXN)DEQ[1:0]URX1N (LN0RXN)DRX1N
HHHLHDEQ[1:0]DRX2PURX2P (LN0RXP)DEQ[1:0]URX2P (LN0RXP)DRX2P
DEQ[1:0]DRX2NURX2N (LN0RXN)DEQ[1:0]URX2N (LN0RXN)DRX2N
UEQ[1:0]UTX2P (LN0RXP)DTX2PUEQ[1:0]DTX2PUTX2P (LN0RXP)
UEQ[1:0]UTX2N (LN0RXN)DTX2NUEQ[1:0]DTX2NUTX2N (LN0RXN)
UEQ[1:0]UTX1P (LN0RXP)DTX1PUEQ[1:0]DTX1PUTX1P (LN0RXP)
UEQ[1:0]UTX1N (LN0RXN)DTX1NUEQ[1:0]DTX1NUTX1N (LN0RXN)
DEQ[1:0]DRX1PURX1P (LN0TXP)DEQ[1:0]URX1P (LN0TXP)DRX1P
DEQ[1:0]DRX1NURX1N (LN0TXN)DEQ[1:0]URX1N (LN0TXN)DRX1N
HHHHLUEQ[1:0]UTX2PDTX2P (SSRXP)UEQ[1:0]DTX2P (SSTXP)UTX2P
UEQ[1:0]UTX2NDTX2N (SSRXN)UEQ[1:0]DTX2N (SSTXN)UTX2N
DEQ[1:0]DRX2P (SSTXP)URX2PDEQ[1:0]URX2PDRX2P (SSRXP)
DEQ[1:0]DRX2N (SSTXN)URX2NDEQ[1:0]URX2NDRX2N (SSRXN)
UEQ[1:0]UTX1PDTX1P (LN0RXP)UEQ[1:0]DTX1P (LN0RXP)UTX1P
UEQ[1:0]UTX1NDTX1N(LN0RXN)UEQ[1:0]DTX1N(LN0RXN)UTX1N
DEQ[1:0]DRX1P (LN0TXP)URX1PDEQ[1:0]URX1PDRX1P (LN0TXP)
DEQ[1:0]DRX1N (LN0TXN)URX1NDEQ[1:0]URX1NDRX1N (LN0TXN)
HHHHHUEQ[1:0]UTX1PDTX1P (SSRXP)UEQ[1:0]DTX1P (SSSXP)UTX1P
UEQ[1:0]UTX1NDTX1N (SSRXN)UEQ[1:0]DTX1N (SSSXN)UTX1N
DEQ[1:0]DRX1P (SSTXP)URX1PDEQ[1:0]URX1PDRX1P (SSRXP)
DEQ[1:0]DRX1N (SSTXN)URX1NDEQ[1:0]URX1NDRX1N (SSRXN)
DEQ[1:0]DRX2PURX2P (LN0TXP)DEQ[1:0]URX2P (LN0TXP)DRX2P
DEQ[1:0]DRX2NURX2N (LN0TXN)DEQ[1:0]URX2N (LN0TXN)DRX2N
UEQ[1:0]UTX2P (LN0RXP)DTX2PUEQ[1:0]DTX2PUTX2P (LN0RXP)
UEQ[1:0]UTX2N (LN0RXN)DTX2NUEQ[1:0]DTX2NUTX2N (LN0RXN)