JAJSEO4E July   2012  – January 2018 TPS23751 , TPS23752

PRODUCTION DATA.  

1. 1 特長
2. 2 アプリケーション
3. 3 概要
   1.     Device Images
      1.      代表的なアプリケーション回路
4. 4 改訂履歴
5. 5 Pin Configuration and Functions
   1.     Pin Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 ESD Ratings: Surge
   4. 6.4 Recommended Operating Conditions
   5. 6.5 Thermal Information
   6. 6.6 Electric Characteristics - Controller Section
   7. 6.7 Electrical Characteristics - Sleep Mode (TPS23752 Only)
   8. 6.8 Electrical Characteristics - PoE Interface Section
   9. 6.9 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagrams
   3. 7.3 Feature Description
      1. 7.3.1 Pin Description
   4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
         1. 7.4.1.1 Threshold Voltages
         2. 7.4.1.2 PoE Startup Sequence
         3. 7.4.1.3 Detection
         4. 7.4.1.4 Hardware Classification
         5. 7.4.1.5 Inrush and Startup
         6. 7.4.1.6 Maintain Power Signature
         7. 7.4.1.7 Startup and Converter Operation
         8. 7.4.1.8 PD Hotswap Operation
      2. 7.4.2 Sleep Mode Operation (TPS23752 only)
         1. 7.4.2.1  Converter Controller Features
         2. 7.4.2.2  PWM and VFO Operation; CTL, SRT, and SRD Pin Relationships to Output Load Current
         3. 7.4.2.3  Bootstrap Topology
         4. 7.4.2.4  Current Slope Compensation and Current Limit
         5. 7.4.2.5  RT
         6. 7.4.2.6  T2P, Startup and Power Management
         7. 7.4.2.7  Thermal Shutdown
         8. 7.4.2.8  Adapter ORing
         9. 7.4.2.9  Using DEN to Disable PoE
         10. 7.4.2.10 ORing Challenges
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1  Input Bridges and Schottky Diodes
         2. 8.2.2.2  Protection, D1
         3. 8.2.2.3  Capacitor, C1
         4. 8.2.2.4  Detection Resistor, RDEN
         5. 8.2.2.5  Classification Resistor, RCLS
         6. 8.2.2.6  APD Pin Divider Network, RAPD1, RAPD2
         7. 8.2.2.7  Setting the PWM-VFO Threshold using the SRT pin
         8. 8.2.2.8  Setting Frequency (RT)
         9. 8.2.2.9  Current Slope Compensation
         10. 8.2.2.10 Voltage Feed-Forward Compensation
         11. 8.2.2.11 Estimating Bias Supply Requirements and Cvc
         12. 8.2.2.12 Switching Transformer Considerations and RVC
         13. 8.2.2.13 T2P Pin Interface
         14. 8.2.2.14 Softstart
         15. 8.2.2.15 Special Switching MOSFET Considerations
         16. 8.2.2.16 ESD
         17. 8.2.2.17 Thermal Considerations and OTSD
      3. 8.2.3 Application Curves
9. 9 Power Supply Recommendations
10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
       1. 11.1.1 関連資料
       2. 11.1.2 関連リンク
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
12. 12メカニカル、パッケージ、および注文情報