JAJSEP3C September   2017  – March 2018 LMZM33603

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     安全動作領域
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 5 V)
    8. 6.8 Typical Characteristics (VIN = 12 V)
    9. 6.9 Typical Characteristics (VIN = 24 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Feed-Forward Capacitor, CFF
      3. 7.3.3  Output Current vs Output Voltage
      4. 7.3.4  Voltage Dropout
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Synchronization (SYNC)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  Output On/Off Enable (EN)
      10. 7.3.10 Programmable Undervoltage Lockout (UVLO)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Feed-Forward Capacitor (CFF)
        4. 8.2.2.4 Setting the Switching Frequency
        5. 8.2.2.5 Input Capacitors
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Theta JA vs PCB Area
    4. 10.4 EMI
      1. 10.4.1 EMI Plots
    5. 10.5 Package Specifications
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 WEBENCH®ツールによるカスタム設計
    2. 11.2 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

5 Pin Configuration and Functions

RLR Package
18-Pin QFN
Top View
LMZM33603 PinPackage4.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 AGND G Analog ground. Zero voltage reference for internal references and logic. Do not connect this pin to PGND; the connection is made internal to the device. See the Layout section of the datasheet for a recommended layout.
2 EN/SYNC I EN - Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. This pin can be used to set the input under voltage lockout with two resistors. See the Programmable Undervoltage Lockout (UVLO) section.
SYNC - The internal oscillator can be synchronized to an external clock via AC-coupling. See the Synchronization (SYNC) section for details.
3 RT I An external timing resistor connected between this pin and AGND adjusts the switching frequency of the device. If left open, the default switching frequency is 400 kHz.
4 VIN I Input supply voltage. Connect external input capacitors between this pin and PGND.
5, 14, 15, 18 PGND G Power ground. This is the return current path for the power stage of the device. Connect pin 5 to the input source, the load, and to the bypass capacitors associated with VIN and VOUT using power ground planes on the PCB. Pins 14 and 15 are not connected to PGND internal to the device and must be connected to PGND at pad 18. Connect pad 18 to the power ground planes using multiple vias for good thermal performance. See the Layout section of the datasheet for a recommended layout.
6, 7, 8 VOUT O Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND.
9, 10, 11 SW O Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not place any external component on these pins or tie them to a pin of another function.
12, 13 DNC — Do not connect. Each pin must be soldered to an isolated pad. These pins connect to internal circuitry. Do not connect these pins to one another, AGND, PGND, or any other voltage.
16 FB I Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND.
17 PGOOD O Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC voltage no higher than 12 V.