JAJSEP3C September   2017  – March 2018 LMZM33603

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     安全動作領域
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 5 V)
    8. 6.8 Typical Characteristics (VIN = 12 V)
    9. 6.9 Typical Characteristics (VIN = 24 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Feed-Forward Capacitor, CFF
      3. 7.3.3  Output Current vs Output Voltage
      4. 7.3.4  Voltage Dropout
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Synchronization (SYNC)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  Output On/Off Enable (EN)
      10. 7.3.10 Programmable Undervoltage Lockout (UVLO)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Feed-Forward Capacitor (CFF)
        4. 8.2.2.4 Setting the Switching Frequency
        5. 8.2.2.5 Input Capacitors
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Theta JA vs PCB Area
    4. 10.4 EMI
      1. 10.4.1 EMI Plots
    5. 10.5 Package Specifications
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 WEBENCH®ツールによるカスタム設計
    2. 11.2 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 38 thru Figure 41, shows a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • Connect PGND pins 14 and 15 directly to pin 18 using thick copper traces.
  • Connect the SW pins together using a small copper island under the device for thermal relief.
  • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Keep AGND and PGND separate from one another.
  • Place RFBT, RFBB, RRT, and CFF as close as possible to their respective pins.
  • Use multiple vias to connect the power planes to internal layers.