JAJSEQ4A February   2018  – April 2018 TPSM84424

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      過渡応答
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Switching Frequency (RT)
      3. 7.3.3  Synchronization (CLK)
      4. 7.3.4  Output On/Off Enable (EN)
      5. 7.3.5  Input Capacitor Selection
      6. 7.3.6  Output Capacitor Selection
      7. 7.3.7  TurboTrans (TT)
        1. 7.3.7.1 Low-ESR Output Capacitors
        2. 7.3.7.2 Transient Response
          1. 7.3.7.2.1 Transient Waveforms (VIN = 12 V)
      8. 7.3.8  Undervoltage Lockout (UVLO)
      9. 7.3.9  Soft Start (SS/TR)
      10. 7.3.10 Sequencing (SS/TR)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Safe Start-up into Pre-Biased Outputs
      13. 7.3.13 Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 Input Capacitors
        5. 8.2.2.5 Output Capacitors
        6. 8.2.2.6 TurboTrans Resistor
        7. 8.2.2.7 Application Waveforms
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 EMI
      1. 10.3.1 EMI Plots
    4. 10.4 Package Specifications
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 開発サポート
      1. 11.2.1 WEBENCH®ツールによるカスタム設計
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

6.5 Electrical Characteristics

Over –40°C to +105°C ambient temperature, VIN = 12 V, VOUT = 1.2 V, IOUT = IOUTmax, fsw = 450 kHz (unless otherwise noted); CIN1 = 2× 10-µF, 25-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4× 47-µF, 10-V, 1210 ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
VIN Input voltage Over IOUT range 4.5(1) 17 V
UVLO VIN undervoltage lockout VIN increasing 4.1 4.3 V
VIN decreasing 3.7 3.9 V
ISHDN Shutdown supply current VEN = 0 V 3 11 µA
OUTPUT VOLTAGE (VOUT)
VOUT(ADJ) Output voltage adjust Over IOUT range 0.6 10 V
VOUT(Ripple) Output voltage ripple 20-MHz bandwidth 16 mV
FEEDBACK
VFB Feedback voltage(2) TA = 25°C, IOUT = 0 A 0.596 0.6 0.604 V
–40°C ≤ TJ ≤ 125°C, IOUT = 0 A 0.595 0.6 0.605 V
Line regulation Over VIN range, TA = 25°C, IOUT = 0 A 0.1 mV
Load regulation Over IOUT range, TA = 25°C 0.8 mV
CURRENT
IOUT Output current Natural convection, TA = 25°C 0 4 A
Overcurrent threshold 11 A
PERFORMANCE
ƞ Efficiency VIN = 12 V,
IOUT = 4 A		 VOUT = 5 V, fSW = 1.2 MHz 94%
VOUT = 3.3 V, fSW = 1.0 MHz 93%
VOUT = 1.8 V, fSW = 600 kHz 91%
VOUT = 1.2 V, fSW = 450 kHz 87%
VOUT = 1 V, fSW = 400 kHz 86%
Transient response
voltage deviation		 25% to 75% load step, 2A/µs slew rate,
RTT = 4.02 kΩ,
COUT = 200-µF ceramic + 220-µF polymer		 27 mV
25% to 75% load step, 2A/µs slew rate,
RTT = 3.40 kΩ, COUT = 200-µF ceramic		 35 mV
SOFT START
tSS Internal soft start time 1.25 ms
ISS Soft start charge current 5 µA
THERMAL
TSHDN Thermal shutdown Shutdown temperature 170 °C
Hysteresis 15 °C
ENABLE (EN)
VEN-H EN rising threshold 1.2 1.26 V
VEN-HYS EN falling threshold 1.1 1.15 V
IEN EN pin sourcing current VEN = 1.1 V 1.2 µA
VEN = 1.3 V 3.6 µA
POWER GOOD (PGOOD)
VPGOOD PGOOD thresholds VOUT rising (fault) 108%
VOUT falling (good) 106%
VOUT rising (good) 91%
VOUT falling (fault) 89%
Minimum VIN for valid PGOOD VPGOOD < 0.5 V, IPGOOD = 2 mA 0.7 1 V
PGOOD low voltage 2-mA pullup, VEN = 0 V 0.3 V
CAPACITANCE
CIN External input capacitance Ceramic type 20(3) µF
Non-ceramic type 100(3) µF
COUT External output capacitance min(4) 1500(5) µF
(1) For output voltages 0.6 V to < 5.5 V, the recommended minimum VIN is 4.5 V or (VOUT + 1 V), whichever is greater. For output voltages 5.5 V to < 9 V, the recommended minimum VIN is (VOUT + 2 V). For output voltages 9 V to 10 V, the recommended minimum VIN is (VOUT + 3 V).
(2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
(3) A minimum of 20-µF ceramic input capacitance is required for proper operation. An additional 100 µF of bulk capacitance is recommended for applications with transient load requirements. See the Input Capacitor section for further guidance.
(4) The minimum amount of required output capacitance varies depending on the output voltage (see Standard Component Values Table). A minimum amount of ceramic output capacitance is required. Locate the capacitance close to the device. Adding additional ceramic or non-ceramic capacitance close to the load improves the response of the regulator to load transients.
(5) The maximum output capacitance can be made up of all ceramic type or a combination of ceramic and a single non-ceramic type. See the Low-ESR Output Capacitors Section for requirements of non-ceramic output capacitors.