JAJSEV7C March   2018  – September 2019 TUSB1064

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      TUSB1064 使用事例
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 ELECTRICAL CHARACTERISTICS
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 11. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 12. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 13. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 14. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 15. DisplayPort Control/Status Registers (0x13)
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 16. USB3.1 Control/Status Registers (0x20)
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 17. USB3.1 Control/Status Registers (0x21)
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
        1. Table 18. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.4.2 Device Configuration In I2C Mode

The TUSB1064 is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO mode are also available in I2C mode. The TUSB1064 USB3.1 and DisplayPort configuration is controlled based on Table 5. The AUXp or AUXn to SBU1 or SBU2 mapping control is based on Table 6.

Table 5. I2C Configuration Control

REGISTERS CONFIGURATION VESA DisplayPort ALT MODE
UFP_D CONFIGURATION
CTLSEL1 CTLSEL0 FLIPSEL
0 0 0 Power Down —
0 0 1 Power Down —
0 1 0 One Port USB 3.1 - No Flip —
0 1 1 One Port USB 3.1 – With Flip —
1 0 0 4 Lane DP - No Flip C
1 0 1 4 Lane DP – With Flip C
1 1 0 One Port USB 3.1 + 2 Lane DP- No Flip D
1 1 1 One Port USB 3.1 + 2 Lane DP– With Flip D

Table 6. I2C AUXp or AUXn to SBU1 or SBU2 Mapping

REGISTERS MAPPING
AUX_SBU_OVR CTLSEL1 FLIPSEL
00 1 0 SBU1 → AUXn
SBU2 → AUXp
00 1 1 SBU2 → AUXn
SBU1 → AUXp
00 0 X Open
01 X X SBU1 → AUXn
SBU2 → AUXp
10 X X SBU2 → AUXn
SBU1 → AUXp
11 X X Open