ADS122C04 24ビット、4チャネル、2kSPS、I2Cインターフェイス搭載のデルタ-シグマADC

1 特長

• 315µA (標準値)の低消費電流
• 広い電源電圧範囲：2.3V～5.5V
• プログラマブル・ゲイン：1～128
• プログラマブル・データ・レート：最大2kSPS
• 最大20ビットの有効分解能
• シングル・サイクル安定化デジタル・フィルタによる50Hzおよび60Hzの同時リジェクション(20SPS)
• 2つの差動入力または4つのシングルエンド入力
• デュアル・マッチのプログラム可能電流源：
  10µA～1.5mA
• 内部リファレンス：2.048V、ドリフト(標準値)：5ppm/℃
• 内部オシレータ：精度2%
• 内部温度センサ：精度0.5℃(標準値)
  
• I²C互換インターフェイス
• サポートされるI²Cバス速度モード:
  Standard-Mode、Fast-Mode、Fast-Mode Plus
• 16のI²Cアドレスをピンで設定可能
• パッケージ：3.0mm × 3.0mm × 0.75mm WQFN

2 アプリケーション

• フィールド・トランスミッタ:
  温度、圧力、張力、フロー
• PLCおよびDCSアナログ入力モジュール
• 温度コントローラ
• 熱メータ
• 患者モニタリング・システム：体温、血圧
  

3 概要

ADS122C04は、高精度の24ビット、アナログ/デジタル・コンバータ(ADC)で、小信号を測定するセンサ・アプリケーションのシステム・コストと部品点数を削減する多数の機能を統合しています。このデバイスは、柔軟な入力マルチプレクサ(MUX)を介した2つの差動入力または4つのシングルエンド入力、低ノイズのプログラマブル・ゲイン・アンプ(PGA)、2つのプログラマブル励起電流源、基準電圧、オシレータ、高精度温度センサを備えています。

このデバイスはシングル・サイクル安定化により、最大2000サンプル/秒(SPS)のデータ・レートで変換を実行します。デジタル・フィルタはノイズの大きい工業用アプリケーションに対して、20SPSで50Hzおよび60Hzの同時リジェクションを提供します。内部PGAは最大128のゲインを提供します。このPGAを備えたADS122C04は、測温抵抗体(RTD)、熱電対、サーミスタ、抵抗性ブリッジ・センサなどの小信号を測定するセンサ・アプリケーションに最適です。

1. 提供されているすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。

Device Images

Kタイプ熱電対温度の測定

4 改訂履歴

Changes from A Revision (March 2018) to B Revision

• Changed Internal Voltage Reference, Accuracy parameter: added TSSOP package to test conditions of first row and added second row for the WQFN package Go
• Added TSSOP package to conditions of Internal Reference Voltage Histogram figureGo
• Changed Digital Supply Current vs Temperature figureGo
• Deleted last sentence from first paragraph of Pseudo Code Example sectionGo
• Changed (MUX[3:1] = 1110) to (MUX[3:0] = 1110) in Pseudo Code Example section Go

Changes from * Revision (October 2017) to A Revision

• 量産用にリリースGo

5 概要（続き）

ADS122C04には2線式のI²C互換インターフェイスが搭載され、最高1MbpsのI²Cバス速度に対応します。2本のアドレス・ピンにより、16の異なるデバイスI²Cアドレスを選択できます。

ADS122C04は、16ピンのリードレスWQFNパッケージ、または16ピンTSSOPパッケージで提供されており、温度範囲-40℃～+125℃で動作が規定されています。

6 Pin Configuration and Functions

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 I²C Timing Requirements

7.7 I²C Switching Characteristics

Figure 1. I²C Timing Requirements

Figure 2. RESET Pin Timing Requirements

Figure 3. DRDY Pin Timing Requirements and Switching Characteristics

7.8 Typical Characteristics

Normal mode, PGA disabled, VIN = 0 V

Figure 4. Absolute Input current vs Absolute Input Voltage

Turbo mode, PGA disabled, VIN = 0 V

Figure 6. Absolute Input Current vs Absolute Input Voltage

Normal mode, PGA disabled, VCM = 1.65 V

Figure 8. Differential Input Current vs
Differential Input Voltage

Turbo mode, PGA disabled, VCM = 1.65 V

Figure 10. Differential Input Current vs
Differential Input Voltage

PGA enabled, external reference, best fit

Figure 12. INL vs Differential Input Voltage

PGA enabled, gain = 1, 620 samples

Figure 14. Offset Voltage Histogram

PGA enabled

Figure 16. Input Offset Voltage vs Temperature

PGA enabled, gain = 1, 620 samples

Figure 18. Gain Error Histogram

PGA disabled

Figure 20. Gain Error vs Temperature

PGA disabled

Figure 22. DC CMRR vs Temperature

5940 samples, TSSOP package

Figure 24. Internal Reference Voltage Histogram

Figure 26. Internal Reference Voltage vs AVDD

Normal mode

Figure 28. Internal Oscillator Frequency Histogram

Normal mode

Figure 30. Internal Oscillator Frequency vs DVDD

Figure 32. IDAC Accuracy vs Temperature

Figure 34. Internal Temperature Sensor Accuracy vs Temperature

Power-down mode

Figure 36. Analog Supply Current vs Temperature

Normal mode

Figure 38. Analog Supply Current vs AVDD

Normal mode

Figure 40. Digital Supply Current vs Temperature

Normal mode, PGA enabled, VIN = 0 V

Figure 5. Absolute Input Current vs Absolute Input Voltage

Turbo mode, PGA enabled, VIN = 0 V

Figure 7. Absolute Input Current vs Absolute Input Voltage

Normal mode, PGA enabled, VCM = 1.65 V

Figure 9. Differential Input Current vs
Differential Input Voltage

Turbo mode, PGA enabled, VCM = 1.65 V

Figure 11. Differential Input Current vs
Differential Input Voltage

PGA enabled, internal reference, best fit

Figure 13. INL vs Differential Input Voltage

PGA disabled

Figure 15. Input Offset Voltage vs Temperature

PGA disabled, gain = 1, 620 samples

Figure 17. Gain Error Histogram

PGA enabled, gain = 128, 620 samples

Figure 19. Gain Error Histogram

PGA enabled

Figure 21. Gain Error vs Temperature

PGA enabled

Figure 23. DC CMRR vs Temperature

Figure 25. Internal Reference Voltage vs Temperature

Figure 27. External Reference Input Current vs Temperature

Normal mode

Figure 29. Internal Oscillator Frequency vs Temperature

Figure 31. IDAC Accuracy vs Compliance Voltage

Figure 33. IDAC Matching vs Temperature

DVDD = 3.3 V

Figure 35. Digital Pin Output Voltage vs Sinking Current

Normal mode

Figure 37. Analog Supply Current vs Temperature

Power-down mode

Figure 39. Digital Supply Current vs Temperature

Normal mode

Figure 41. Digital Supply Current vs DVDD

8 Parameter Measurement Information

8.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 1 to Table 8 summarize the device noise performance. Data are representative of typical noise performance at T_A = 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings from a single device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted together. Table 1, Table 3, Table 5, and Table 7 list the input-referred noise in units of μV_RMS for the conditions shown. Values in µV_PP are shown in parenthesis. Table 2, Table 4, Table 6, and Table 8 list the corresponding data in effective resolution calculated from μV_RMS values using Equation 1. Noise-free resolution calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

The input-referred noise (Table 1, Table 3, Table 5, and Table 7) only changes marginally when using an external low-noise reference, such as the REF5020. Use Equation 1 and Equation 2 to calculate effective resolution numbers and noise-free resolution when using a reference voltage other than 2.048 V:

9 Detailed Description

9.1 Overview

The ADS122C04 is a small, low-power, 24-bit, ΔΣ ADC that offers many integrated features to reduce system cost and component count in applications measuring small sensor signals.

In addition to the ΔΣ ADC core and single-cycle settling digital filter, the device offers a low-noise, high input impedance, programmable gain amplifier (PGA), an internal 2.048-V voltage reference, and a clock oscillator. The device also integrates a highly linear and accurate temperature sensor as well as two matched programmable current sources (IDACs) for sensor excitation. All of these features are intended to reduce the required external circuitry in typical sensor applications and improve overall system performance. The device is fully configured through four registers and controlled by six commands through an I²C-compatible interface. The Functional Block Diagram section shows the device functional block diagram.

The ADS122C04 ADC measures a differential signal, V_IN, which is the difference in voltage between nodes AIN_P and AIN_N. The converter core consists of a differential, switched-capacitor, ΔΣ modulator followed by a digital filter. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. This architecture results in a very strong attenuation of any common-mode signal.

The device has two available conversion modes: single-shot conversion and continuous conversion mode. In single-shot conversion mode, the ADC performs one conversion of the input signal upon request and stores the value in an internal data buffer. The device then enters a low-power state to save power. Single-shot conversion mode is intended to provide significant power savings in systems that require only periodic conversions, or when there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. New data are available at the programmed data rate. Data can be read at any time without concern of data corruption and always reflect the most recently completed conversion.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Multiplexer

Figure 42 shows the flexible input multiplexer of the device. Either four single-ended signals, two differential signals, or a combination of two single-ended signals and one differential signal can be measured. The multiplexer is configured by four bits (MUX[3:0]) in the configuration register. When single-ended signals are measured, the negative ADC input (AIN_N) is internally connected to AVSS by a switch within the multiplexer. For system-monitoring purposes, the analog supply [(AVDD – AVSS) / 4] or the currently selected external reference voltage [(V_REFP – V_REFN) / 4] can be selected as inputs to the ADC. The multiplexer also offers the possibility to route any of the two programmable current sources to any analog input (AINx) or to the dedicated reference pins (REFP, REFN).

Figure 42. Analog Input Multiplexer

Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. The absolute voltage on any input must stay within the range provided by Equation 3 to prevent the ESD diodes from turning on:

If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Overdriving an unused input on the device can affect conversions taking place on other input pins.

9.3.2 Low-Noise Programmable Gain Stage

The device features programmable gains of 1, 2, 4, 8, 16, 32, 64, and 128. Three bits (GAIN[2:0]) in the configuration register are used to configure the gain. Gains are achieved in two stages. The first stage is a low-noise, low-drift, high input impedance, programmable gain amplifier (PGA). The second gain stage is implemented by a switched-capacitor circuit at the input to the ΔΣ modulator. Table 9 shows how each gain is implemented.

The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the PGA gain. The input is equipped with an electromagnetic interference (EMI) filter. Figure 43 shows a simplified diagram of the PGA.

Figure 43. Simplified PGA Diagram

V_IN denotes the differential input voltage V_IN = V_AINP – V_AINN. Use Equation 4 to calculate the gain of the PGA. Gain is changed inside the device using a variable resistor, R_G.

The switched-capacitor gain is changed using variable capacitors at the input to the ΔΣ modulator. Gains 1, 2, and 4 are implemented by using only the switched-capacitor circuit, which allows these gains to be used even when the PGA is bypassed; see the Bypassing the PGA section for more information about bypassing the PGA.

Equation 5 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gain setting and the reference voltage used:

Table 10 shows the corresponding full-scale ranges when using the internal 2.048-V reference.

9.3.2.1 PGA Input Voltage Requirements

As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded. The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA output. The specified minimum and maximum absolute input voltages (V_AINP and V_AINN) depend on the PGA gain, the maximum differential input voltage (V_INMAX), and the tolerance of the analog power-supply voltages (AVDD and AVSS). Because gain on the ADS122C04 is implemented by both the PGA and a switched-capacitor gain circuit, there are two formulas that define the absolute input voltages. Use Equation 6 when the device gain is configured to less than or equal to 4. Use Equation 7 when the device gain is greater than 4. Use the maximum differential input voltage expected in the application for V_INMAX.

Figure 44 graphically shows the relationship between the PGA input voltages to the PGA output voltages for gains larger than 4. The PGA output voltages (V_OUTP, V_OUTN) depend on the PGA gain and the differential input voltage magnitudes. For linear operation, the PGA output voltages must not exceed AVDD – 0.2 V or AVSS + 0.2 V. Figure 44 depicts an example of a positive differential input voltage that results in a positive differential output voltage.

Figure 44. PGA Input/Output Voltage Relationship

9.3.2.2 Bypassing the PGA

At gains of 1, 2, and 4, the device can be configured to disable and bypass the low-noise PGA by setting the PGA_BYPASS bit in the configuration register. Disabling the PGA lowers the overall power consumption and also removes the restrictions of Equation 6 and Equation 7 for the absolute input voltage range. The usable absolute input voltage range is (AVSS – 0.1 V ≤ V_AINP, V_AINN ≤ AVDD + 0.1 V) when the PGA is disabled.

In order to measure single-ended signals that are referenced to AVSS (AIN_P = V_IN, AIN_N = AVSS), the PGA must be bypassed. Configure the device for single-ended measurements by either connecting one of the analog inputs to AVSS externally or by using the internal AVSS connection of the multiplexer (MUX[3:0] settings 1000 through 1011). When configuring the internal multiplexer for settings where AIN_N = AVSS (MUX[3:0] = 1000 through 1011), the PGA is automatically bypassed and disabled irrespective of the PGA_BYPASS setting and gain is limited to 1, 2, and 4. In case gain is set to greater than 4, the device limits gain to 4.

When the PGA is disabled, the device uses a buffered switched-capacitor stage to obtain gains 1, 2, and 4. An internal buffer in front of the switched-capacitor stage ensures that the effect on the input loading resulting from the capacitor charging and discharging is minimal. See the Electrical Characteristics section for the typical values of absolute input currents (current flowing into or out of each input) and differential input currents (difference in absolute current between the positive and negative input) when the PGA is disabled.

For signal sources with high output impedance, external buffering may still be necessary. Active buffers can introduce noise as well as offset and gain errors. Consider all of these factors in high-accuracy applications.

9.3.3 Voltage Reference

The device offers an integrated, low-drift, 2.048-V reference. For applications that require a different reference voltage value or a ratiometric measurement approach, the device offers a differential reference input pair (REFP and REFN). In addition, the analog supply (AVDD – AVSS) can be used as a reference.

The reference source is selected by two bits (VREF[1:0]) in the configuration register. By default, the internal reference is selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when coming out of power-down mode, or when switching from an external reference source to the internal reference.

The differential reference input allows freedom in the reference common-mode voltage. The reference inputs are internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required when using an external reference. When used in ratiometric applications, the reference inputs do not load the external circuitry; however, the analog supply current increases when using an external reference because the reference buffers are enabled.

In most cases the conversion result is directly proportional to the stability of the reference source. Any noise and drift of the voltage reference is reflected in the conversion result.

9.3.4 Modulator and Internal Oscillator

A ΔΣ modulator is used in the ADS122C04 to convert the analog input voltage into a pulse code modulated (PCM) data stream. The modulator runs at a modulator clock frequency of f_MOD = f_CLK / 4, where f_CLK is provided by the internal oscillator. The oscillator frequency, and therefore also the modulator frequency, depend on the selected operating mode. Table 11 shows the oscillator and modulator frequencies for the different operating modes.

9.3.5 Digital Filter

The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the different data rates and always settles within a single cycle. The frequency responses of the digital filter are illustrated in Figure 45 to Figure 53 for different output data rates. The filter notches and output data rate scale proportionally with the clock frequency. The internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate or conversion time, respectively, and consequently also the filter notches vary proportionally.

Figure 45. Filter Response
(Normal Mode, DR = 20 SPS)

Figure 47. Filter Response
(Normal Mode, DR = 45 SPS)

Figure 46. Detailed View of the Filter Response
(Normal Mode, DR = 20 SPS)

Figure 48. Filter Response
(Normal Mode, DR = 90 SPS)

Figure 49. Filter Response
(Normal Mode, DR = 175 SPS)

Figure 51. Filter Response
(Normal Mode, DR = 600 SPS)

Figure 53. Filter Response
(Turbo Mode, DR = 2 kSPS)

Figure 50. Filter Response
(Normal Mode, DR = 330 SPS)

Figure 52. Filter Response
(Normal Mode, DR = 1 kSPS)

9.3.6 Conversion Times

Table 12 shows the actual conversion times for each data rate setting. The values provided are in terms of t_CLK cycles and in milliseconds.

Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge. The first conversion starts 28.5 · t_CLK (normal mode) or 105 · t_CLK (turbo mode) after the START/SYNC command is latched.

Single-shot conversion mode data rates are timed from when the START/SYNC command is latched to the DRDY falling edge and rounded to the next t_CLK.

Commands are latched on the eighth falling edge of SCL in the command byte.

Although the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does not affect the 50-Hz or 60-Hz rejection. The conversion time and filter notches vary by the amount specified in the Electrical Characteristics table for oscillator accuracy.

9.3.7 Excitation Current Sources

The device provides two matched programmable excitation current sources (IDACs) for resistance temperature detector (RTD) applications. The output current of the current sources can be programmed to 10 µA, 50 µA, 100 µA, 250 µA, 500 µA, 1000 µA, or 1500 µA using the respective bits (IDAC[2:0]) in the configuration register. Each current source can be connected to any of the analog inputs (AINx) as well as to the dedicated reference inputs (REFP and REFN). Both current sources can also be connected to the same pin. Routing of the IDACs is configured by bits (I1MUX[2:0], I2MUX[2:0]) in the configuration register. Care must be taken not to exceed the compliance voltage of the IDACs. In other words, limit the voltage on the pin where the IDAC is routed to ≤ (AVDD – 0.9 V), otherwise the specified accuracy of the IDAC current is not met. For three-wire RTD applications, the matched current sources can be used to cancel errors caused by sensor lead resistance (see the 3-Wire RTD Measurement section for more details).

The IDACs require up to 200 µs to start up after the IDAC current is programmed to the respective value using the IDAC[2:0] bits. Set the IDAC current to the respective value using the IDAC[2:0] bits and then select the routing for each IDAC (I1MUX[2:0], I2MUX[2:0]) thereafter.

In single-shot conversion mode, the IDACs remain active between any two conversions if the IDAC[2:0] bits are set to a value other than 000. However, the IDACs are powered down whenever the POWERDOWN command is issued.

Keep in mind that the analog supply current increases when enabling the IDACs (that is, when the IDAC[2:0] bits are set to a value other than 000). The IDAC circuit needs this bias current to operate even when the IDACs are not routed to any pin (I1MUX[2:0] = I2MUX[2:0] = 000). In addition, the selected output current is drawn from the analog supply when I1MUX[2:0] or I2MUX[2:0] are set to a value other than 000.

9.3.8 Sensor Detection

To help detect a possible sensor malfunction, the device provides internal 10-µA, burn-out current sources. When enabled by setting the respective bit (BCS) in the configuration register, one current source provides current to the positive analog input (AIN_P) currently selected and the other current source sinks current from the selected negative analog input (AIN_N).

In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading can also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading can indicate a shorted sensor. The absolute value of the burn-out current sources typically varies by ±5% and the internal multiplexer adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero.

Keep in mind that ADC readings of a functional sensor may be corrupted when the burn-out current sources are enabled. Disable the burn-out current sources when preforming the precision measurement, and only enable these sources to test for sensor fault conditions.

9.3.9 System Monitor

The device provides some means for monitoring the analog power supply and the external voltage reference. To select a monitoring voltage, the internal multiplexer (MUX[3:0]) must be configured accordingly in the configuration register. The device automatically bypasses the PGA and sets the gain to 1, irrespective of the configuration register settings when the monitoring feature is used. The system monitor function only provides a coarse result and is not meant to be a precision measurement.

When measuring the analog power supply (MUX[3:0] = 1101), the resulting conversion is approximately (AVDD – AVSS) / 4. The device uses the internal 2.048-V reference for the measurement regardless of what reference source is selected in the configuration register (VREF[1:0]).

When monitoring the external reference voltage source (MUX[3:0] = 1100), the result is approximately (V_(REFP) – V_(REFN)) / 4. The device automatically uses the internal reference for the measurement.

9.3.10 Temperature Sensor

The ADS122C04 offers an integrated precision temperature sensor. The temperature sensor mode is enabled by setting the TS bit = 1 in the configuration register. When in temperature sensor mode, the settings of configuration register 0 have no effect and the device uses the internal reference for measurement, regardless of the selected voltage reference source. Temperature readings follow the same process as the analog inputs for starting and reading conversion results. Temperature data are represented as a 14-bit effective result that is left-justified within the 24-bit conversion result. When reading the three data bytes, the first 14 bits (MSBs) are used to indicate the temperature measurement result. The LSBs of the data output do not indicate temperature. Only the 14 MSBs are relevant. One 14-bit LSB equals 0.03125°C. Negative numbers are represented in binary two's complement format. Table 13 shows the mapping between temperature and digital codes.

9.3.10.1 Converting From Temperature to Digital Codes

9.3.10.1.1 For Positive Temperatures (For Example, 50°C):

Two's complement is not performed on positive numbers. Therefore, simply convert the number to binary code in a 14-bit, left-justified format with the MSB = 0 to denote the positive sign.

Example: 50°C / (0.03125°C per count) = 1600 = 0640h = 00 0110 0100 0000

9.3.10.1.2 For Negative Temperatures (For Example, –25°C):

Generate the two's complement of a negative number by complementing the absolute binary number and adding 1. Then, denote the negative sign with the MSB = 1.

Example: |–25°C| / (0.03125°C per count) = 800 = 0320h = 00 0011 0010 0000

Two's complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000

9.3.10.2 Converting From Digital Codes to Temperature

To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0, simply multiply the decimal code by 0.03125°C to obtain the result. If the MSB is a 1, subtract 1 from the result and complement all bits. Then, multiply the result by –0.03125°C.

Example: The device reads back 0960h: 0960h has an MSB = 0.

0960h · 0.03125°C = 2400 · 0.03125°C = 75°C

Example: The device reads back 3CE0h: 3CE0h has an MSB = 1.

Subtract 1 and complement the result: 3CE0h → 0320h

0320h · (–0.03125°C) = 800 · (–0.03125°C) = –25°C

9.3.11 Offset Calibration

The internal multiplexer offers the option to short both PGA inputs (AIN_P and AIN_N) to mid-supply (AVDD + AVSS) / 2. This option can be used to measure and calibrate the device offset voltage by storing the result of the shorted input voltage reading in a microcontroller and consequently subtracting the result from each following reading. Take multiple readings with the inputs shorted and average the result to reduce the effect of noise.

9.3.12 Conversion Data Counter

The ADS122C04 offers an optional data counter word to help the host determine if the conversion data are new. The DCNT bit in the configuration register enables the conversion data counter. The data counter appears as an 8-bit word that precedes the conversion data each time a conversion result is read. The reset value of the counter is 00h. The word increments each time the ADC completes a conversion. The counter rolls over to 00h after reaching FFh.

When the host reads a conversion result, the host can determine if the data being read are new by comparing the counter value with the counter value obtained with the last data read. If the counter values are the same, then this result indicates that no new conversion data are available from the ADC. The counter can also help the host determine if a conversion result was missed.

Reset the conversion data counter by clearing the DCNT bit to 0 and then setting DCNT back to 1. A device reset also resets the conversion data counter.

9.3.13 Data Integrity Features

There are two methods for ensuring data integrity for data output on the ADS122C04. Output data can be register contents or conversion results. The optional data counter word that precedes conversion data is covered by both data integrity options. The data integrity modes are configured using the CRC[1:0] bits in the configuration register. When CRC[1:0] = 01, a bitwise-inverted version of the data is output immediately following the most significant byte (MSB) of the data.

When CRC[1:0] = 10, a 16-bit CRC word is output immediately following the MSB of the data. In CRC mode, the checksum bytes are the 16-bit remainder of the bitwise exclusive-OR (XOR) of the data bytes with a CRC polynomial. The CRC is based on the CRC-16-CCITT polynomial: x¹⁶ + x¹² + x⁵ + 1 with an initial value of FFFFh.

The 17 binary coefficients of the polynomial are: 1 0001 0000 0010 0001. To calculate the CRC, divide (XOR operation) the data bytes (excluding the CRC) with the polynomial and compare the calculated CRC values to the ADC CRC value. If the values do not match, a data transmission error has occurred. In the event of a data transmission error, read the data again.

The following list shows a general procedure to compute the CRC value:

1. Left-shift the initial data value by 16 bits, with zeros padded to the right.
2. Align the MSB of the CRC polynomial to the left-most, logic-one value of the data.
3. Perform an XOR operation on the data value with the aligned CRC polynomial. The XOR operation creates a new, shorter-length value. The bits of the data values that are not in alignment with the CRC polynomial drop down and append to the right of the new XOR result.
4. When the XOR result is less than 1 0000 0000 0000 0000, the procedure ends, yielding the 16-bit CRC value. Otherwise, continue with the XOR operation shown in step 2 using the current data value. The number of loop iterations depends on the value of the initial data.

9.4 Device Functional Modes

Figure 54 shows a flow chart of the different operating modes and how the device transitions from one mode to another.

1. Any reset (power-on, command, or pin) immediately resets the device.

2. The conversion mode is selected with the CM bit in the configuration register.

3. The POWERDOWN command allows any ongoing conversion to complete before placing the device in power-down mode.

Figure 54. Operating Flow Chart

9.4.1 Power-Up and Reset

The ADS122C04 is reset in one of three ways: either by a power-on reset, by the RESET pin, or by a RESET command.

When a reset occurs, the configuration registers reset to the default values and the device enters a low-power state. The device then waits for the START/SYNC command to enter conversion mode; see the I2C Timing Requirements table for reset timing information.

9.4.1.1 Power-On Reset

During power up, the device is held in reset. The power-on reset releases approximately 500 µs after both supplies have exceeded their respective power-up reset thresholds. After this time all internal circuitry (including the voltage reference) are stable and communication with the device is possible. As part of the power-on reset process, the device sets all bits in the configuration registers to the respective default settings. After power-up, the device enters a low-power state. This power-up behavior is intended to prevent systems with tight power-supply requirements from encountering a current surge during power-up.