JAJSF24C March   2018  – July 2024 TUSB1002A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Adjustable VOD Linear Range and DC Gain
      4. 6.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
      5. 6.3.5 USB3.2 Single Channel Operation (MODE = “1”)
      6. 6.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
      7. 6.3.7 Basic Redriver Operation (MODE = “0”)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
    5. 6.5 U0 Mode
    6. 6.6 U1 Mode
    7. 6.7 U2/U3 Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical USB3.2 Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 ESD Protection
      4. 7.2.4 Application Curves
    3. 7.3 Typical SATA, PCIe and SATA Express Application
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curves
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tIDLEEntryDelay from U0 to electrical idleVCC = 3.0V; EN = 1; See Figure 5-1150ps
tIDLEEntry_U1U1 exit time. Break in electrical idle to transmission of LFPS.VCC = 3.0V; EN = 1; See Figure 5-1150ps
tIDLEEntry_U2U3U2/U3 exit time; Break in electrical idle to transmission of LFPSVCC = 3.0V; EN = 1; See Figure 5-16µs
tDIFF_DLYDifferential propagation delayVCC = 3.0V; EN = 1;150ps
tPWRUP_ACTIVETime from assertion of EN to device active and performing Rx.Detect on both portsVCC = 3.0V; EN = 1;8ms
tTX_RISE_FALLTransmitter rise/fall timeVCC = 3.3V; EN = 1; 10Gbps; 20% to 80% of differential output; 1200mVpp linear range setting; Fast Input rise/fall time;27ps
tRF_MISMATCHTransmitter rise/fall mismatchVCC = 3.3V; EN = 1; 10Gbps; 20% to 80% of differential output; 1200mVpp linear range setting; 1000mVpp VID.6ps
tTX_DJTransmitter residual deterministic jitterVCC = 3.3V; EN = 1; 10Gbps; 1200mVpp linear range setting;  Input channel loss of 12dB; Output channel loss of 1.5dB; Optimized EQ;0.05UI
TUSB1002A Idle Entry and Exit Latency Figure 5-1 Idle Entry and Exit Latency
TUSB1002A Power-Up Diagram Figure 5-2 Power-Up Diagram