The MODE pin = "R", CFG1 = "0", and CFG2 = "0" places the TUSB1002A into PCIe mode. In this mode, the TUSB1002A DC gain is fixed at 0dB and its linearity range is fixed at 1200mV. The TUSB1002A performs far-end receiver termination detection and enables both upstream and downstream paths when far-end termination is detected on both TX1 and TX2.

The AC coupling capacitor range defined for a SATA device is a lot smaller than the AC-coupling capacitor range defined for SATA Express and PCI Express (PCIe) as indicated by Figure 7-5. The AC-coupling capacitor range defined for SATA Express and PCI Express is within the same range as the AC-coupling capacitor range defined by USB 3.1. The TUSB1002A is able to detect PCIe and SATA Express device's receiver termination. The SATA 12nF (maximum) AC-coupling capacitor prevents TUSB1002A from detecting the SATA device receiver termination. To correct this problem, a ferrite bead along with 49.9Ω resistor must be placed between C_TX2 and miniCard/mSATA socket. These components can be isolated from the high-speed channel when PCIe or SATA Express is active by using an NFET as shown in Figure 7-6. The NFET is enabled whenever a SATA device is present. The ferrite bead chosen must present at least 600Ω impedance at 100MHz so as to not impact high-speed signaling. TI recommends to use Murata BLM03AG601SN1 or BLM03HD601SN1D or a ferrite bead with similar characteristics from a different vendor. For applications which only require support for PCIe and SATA Express and do not need to support SATA, the ferrite beads and 49.9Ω resistors are not needed.

The TUSB1002A power is at P_{(U0_SSP_1200mV)} when both its upstream and downstream paths are enabled. In order to save system power in system S3/S4/S5 states, it is suggested to control the TUSB1002A EN pin. Anytime the system enters a low power state (S3, S4, or S5), it is suggested to deassert the EN pin. While EN pin is deasserted, the TUSB1002A consumes P_(SHUTDOWN). Assertion of this pin is necessary anytime the system exits a lower power state.

The TUSB1002A compensates for channel loss in both the upstream (C to D) and downstream direction (A to B). This is done by configurable the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as close possible to the channel insertion loss. In this particular example, CH2_EQ[2:1] is for path A to B which is the channel between PCIe/SATA/SATA Express host and the TUSB1002A, and CH1_EQ[2:1] is for path C to D which is the channel between TUSB1002A and the miniCard/mSATA socket.

In this particular example, the channel A-B has a trace length of 8 inches with a 4mil trace width. This particular channel has about 0.83dB per inch of insertion loss at 5GHz. This equates to approximately 6.7dB of loss for the entire 8 inches of trace as depicted in Figure 7-3. An additional 1.5dB of loss is added due to package of the PCIe/SATA/SATA Express Host, TUSB1002A, and the A/C coupling capacitor. This brings the entire channel loss at 5GHz to 6.7dB + 1.5dB = 8.2dB. The channel A-B for this example is connected to the TUSB1002A RX2P/N input, therefore the CH2_EQ[2:1] pins are used to adjust the TUSB1002A RX2P/N equalization settings. Set the CH2_EQ[2:1] pins such that the TUSB1002A equalization is between 5dB and 8dB. A value closer to 5dB maybe best if Host has transmitter de-emphasis.

A similar method can be used for the upstream path (C to D). In this particular example, C to D has a trace length of 2 inches with a 4mil trace width. This equates to approximately 1.5dB at 5GHz. The SATA/SATA Express/PCIe device will also have channel loss. This loss can be added to the C to D channel loss. For this example, assume a value of 5dB is acceptable to compensate for C to D channel loss as well as loss associated with the SATA/SATA Express/PCIe device. Set the CH1_EQ[2:1] pins such that the TUSB1002A equalization is 5dB.