JAJSF24C March   2018  – July 2024 TUSB1002A

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Adjustable VOD Linear Range and DC Gain
      4. 6.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
      5. 6.3.5 USB3.2 Single Channel Operation (MODE = “1”)
      6. 6.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
      7. 6.3.7 Basic Redriver Operation (MODE = “0”)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
    5. 6.5 U0 Mode
    6. 6.6 U1 Mode
    7. 6.7 U2/U3 Mode
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical USB3.2 Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 ESD Protection
      4. 7.2.4 Application Curves
    3. 7.3 Typical SATA, PCIe and SATA Express Application
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curves
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Layout Guidelines

  • Route RXP/N and TXP/N pairs with controlled 90Ω differential impedance (±15%).
  • Keep away from other high speed signals.
  • In USB3 applications maintaining polarity through the TUSB1002A is not necessary. Therefore, TI recommends connecting polarity in such a way that produces the best routing.
  • Keep intra-pair routing to within 2mils.
  • Intra-pair length matching must be near the location of mismatch.
  • Inter-pair length matching is not necessary.
  • Separate each pair at least by 3 times the signal trace width.
  • Keep the use of bends in differential traces to a minimum. When bends are used, keep the number of left and right bends equal as possible and the angle of the bend should be ≥ 135 degrees. This minimizes any length mismatch causes by the bends; ad therefore, minimize the impact bends have on EMI.
  • Route all differential pairs on the same of layer.
  • The number of VIAS must be kept to a minimum. TI recommends keeping the VIAS count to 2 or less.
  • Keep traces on layers adjacent to ground plane.
  • Do NOT route differential pairs over any plane split.
  • When using thru-hole USB connectors, it is recommend to route differential pairs on bottom layer in order to minimize the stub created by the thru-hole connector.
  • Adding Test points causes impedance discontinuity; and therefore, negatively impact signal performance. If test points are used, place the test points in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.