JAJSF35D September   2017  – October 2019 TPS50601A-SP

PRODUCTION DATA.  

  1. 1 特長
    1.     VIN＝PVIN＝5Vでの効率
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Slope Compensation
      7. 8.3.7  Enable and Adjust UVLO
      8. 8.3.8  Adjustable Switching Frequency and Synchronization (SYNC)
      9. 8.3.9  Slow Start (SS/TR)
      10. 8.3.10 Power Good (PWRGD)
      11. 8.3.11 Sequencing (SS/TR)
      12. 8.3.12 Output Overvoltage Protection (OVP)
      13. 8.3.13 Overcurrent Protection
        1. 8.3.13.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.13.2 Low-Side MOSFET Overcurrent Protection
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Turn-On Behavior
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Slow Start Capacitor Selection
        5. 9.2.2.5 Undervoltage Lockout (UVLO) Set Point
        6. 9.2.2.6 Output Voltage Feedback Resistor Selection
        7. 9.2.2.7 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.3.8 Adjustable Switching Frequency and Synchronization (SYNC)

The switching frequency of the device supports three modes of operations. The modes of operation are set by the conditions on the RT and SYNC pins. At a high level, these modes can be described as master, internal oscillator, and external synchronization modes.

In master mode, the RT pin should be left floating; the internal oscillator is set to 500 kHz, and the SYNC pin is set as an output clock. The SYNC output is in phase with respect to the internal oscillator. SYNC out signal level is the same as VIN level with 50% duty cycle. SYNC signal feeding the slave module, which is in phase with the master clock, gets internally inverted (180° out of phase with the master clock) internally in the slave module.

In internal oscillator mode, a resistor is connected between the RT pin and GND. The SYNC pin requires a 10-kΩ resistor to GND for this mode to be effective. The switching frequency of the device is adjustable from 100 kHz to 1 MHz by placing a maximum of 510 kΩ and a minimum of 47 kΩ respectively. To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 18. To reduce the solution size, the designer should set switching frequency as high as possible, but consider the tradeoffs of supply efficiency and minimum controllable on-time.

Equation 4. TPS50601A-SP eq4_rt_lvs949.gif

where

  • RT in kΩ
  • fSW in kHz
TPS50601A-SP rt_vs_freq_lvsa94.gifFigure 18. RT vs Switching Frequency

When operating the converter in internal oscillator mode (internal oscillator determines the switching frequency (500 kHz) default), the synchronous pin becomes the output and there is a phase inversion. When trying to parallel with another converter, the RT pin of the second (slave) converter must have its RT pin populated such that the converter frequency of the slave converter must be within ±5% of the master converter. This is required because the RT pin also sets the proper operation of slope compensation.

In external synchronization mode, a resistor is connected between the RT pin and GND. The SYNC pin requires a toggling signal for this mode to be effective. The switching frequency of the device goes 1:1 with that of SYNC pin. External system clock-user supplied sync clock signal determines the switching frequency. If no external clock signal is detected for 20 µs, then TPS50601A-SP transitions to its internal clock, which is typically 500 kHz. An external synchronization using an inverter to obtain phase inversion is necessary. RT values of the master and slave converter must be within ±5% of the external synchronization frequency. This is necessary for proper slope compensation. A resistance in the RT pin is required for proper operation of the slope compensation circuit. To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 18.

These modes are described in Table 3.

Table 3. Switching Frequency, SYNC and RT Pin Usage Table

RT PIN SYNC PIN SWITCHING FREQUENCY DESCRIPTION AND NOTES
Float Generates an output signal 500 kHz SYNC pin behaves as an output. SYNC output signal is 180° in phase to the internal 500-kHz switching frequency.
47-kΩ to 510-kΩ resistor to AGND 10-kΩ resistor to GND 100 kHz to 1 MHz Internally generated switching frequency is based upon the resistor value present at the RT pin.
User-supplied sync clock or
TPS50601A-SP master device sync output 		Internally synchronized to external clock Set value of RT that corresponds to the externally supplied sync frequency.