JAJSF35D September   2017  – October 2019 TPS50601A-SP

PRODUCTION DATA.  

  1. 1 特長
    1.     VIN＝PVIN＝5Vでの効率
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Slope Compensation
      7. 8.3.7  Enable and Adjust UVLO
      8. 8.3.8  Adjustable Switching Frequency and Synchronization (SYNC)
      9. 8.3.9  Slow Start (SS/TR)
      10. 8.3.10 Power Good (PWRGD)
      11. 8.3.11 Sequencing (SS/TR)
      12. 8.3.12 Output Overvoltage Protection (OVP)
      13. 8.3.13 Overcurrent Protection
        1. 8.3.13.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.13.2 Low-Side MOSFET Overcurrent Protection
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Turn-On Behavior
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Slow Start Capacitor Selection
        5. 9.2.2.5 Undervoltage Lockout (UVLO) Set Point
        6. 9.2.2.6 Output Voltage Feedback Resistor Selection
        7. 9.2.2.7 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.3.10 Power Good (PWRGD)

The PWRGD pin is an open-drain output. When the VSENSE pin is between 94% and 106% of the internal voltage reference, the PWRGD pin pull-down is deasserted and the pin floats. TI recommends to use a pullup resistor between 10 kΩ to 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state when the VIN input voltage is greater than 1 V but has reduced current sinking capability. The PWRGD achieves full current sinking capability when the VIN input voltage is above 3 V.

The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN pin is pulled low or the SS/TR pin is below 1.55 V.