JAJSF35D September   2017  – October 2019 TPS50601A-SP

PRODUCTION DATA.  

  1. 1 特長
    1.     VIN＝PVIN＝5Vでの効率
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Adjusting the Output Voltage
      4. 8.3.4  Safe Start-Up Into Prebiased Outputs
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Slope Compensation
      7. 8.3.7  Enable and Adjust UVLO
      8. 8.3.8  Adjustable Switching Frequency and Synchronization (SYNC)
      9. 8.3.9  Slow Start (SS/TR)
      10. 8.3.10 Power Good (PWRGD)
      11. 8.3.11 Sequencing (SS/TR)
      12. 8.3.12 Output Overvoltage Protection (OVP)
      13. 8.3.13 Overcurrent Protection
        1. 8.3.13.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.13.2 Low-Side MOSFET Overcurrent Protection
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Turn-On Behavior
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Slow Start Capacitor Selection
        5. 9.2.2.5 Undervoltage Lockout (UVLO) Set Point
        6. 9.2.2.6 Output Voltage Feedback Resistor Selection
        7. 9.2.2.7 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

9.2.2.7 Compensation Component Selection

There are several industry techniques used to compensate DC-DC regulators. For this design, type 2B compensation is used as shown in Small Signal Model for Frequency Compensation.

First, the modulator pole, fpmod, and the RESR zero, fzmod must be calculated using Equation 17 and Equation 18. Use Equation 19 and Equation 20 to estimate a starting point for the closed loop crossover frequency fco, then the required compensation components may be derived. For this design example, fpmod is 1.16 kHz and fzmod is 80.38 kHz. Equation 19 is the geometric mean of the modulator pole and the ESR zero and Equation 20 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this case Equation 19 yields 9.65 kHz and Equation 20 yields 7.61 kHz. A frequency of 7.6 kHz is chosen as the intended crossover frequency.

Equation 17. TPS50601A-SP eq_comp5.gif
Equation 18. TPS50601A-SP eq_comp6.gif
Equation 19. TPS50601A-SP eq_comp7.gif
Equation 20. TPS50601A-SP eq_comp8.gif

Now the compensation components can be calculated using Equation 10 and Equation 11. The standard values for R3 and C1 are 1.6 kΩ and 82 nF, respectively.