JAJSF70C July   2015  – July 2024 TUSB4020BI-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 3.3V I/O Electrical Characteristics
    6. 5.6 Hub Input Supply Current
    7. 5.7 Power-Up Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Battery Charging Features
      2. 6.3.2 USB Power Management
      3. 6.3.3 Clock Generation
      4. 6.3.4 Power-Up and Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 External Configuration Interface
    5. 6.5 Programming
      1. 6.5.1 One-Time Programmable (OTP) Configuration
      2. 6.5.2 I2C EEPROM Operation
      3. 6.5.3 SMBus Target Operation
    6. 6.6 Register Maps
      1. 6.6.1 Configuration Registers
        1. 6.6.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 6.6.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 6.6.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 6.6.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 6.6.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 6.6.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 6.6.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 6.6.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 6.6.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 6.6.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 6.6.1.11 Device Configuration Register 2 (offset = Ah)
        12. 6.6.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 6.6.1.13 Language ID LSB Register (offset = 20h)
        14. 6.6.1.14 Language ID MSB Register (offset = 21h)
        15. 6.6.1.15 Serial Number String Length Register (offset = 22h)
        16. 6.6.1.16 Manufacturer String Length Register (offset = 23h)
        17. 6.6.1.17 Product String Length Register (offset = 24h)
        18. 6.6.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 6.6.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 6.6.1.20 Product String Registers (offset = 90h to CFh)
        21. 6.6.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 6.6.1.22 Charging Port Control Register (offset = F2h)
        23. 6.6.1.23 Device Status and Command Register (offset = F8h)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Crystal Requirements
      2. 7.1.2 Input Clock Requirements
    2. 7.2 Typical Applications
      1. 7.2.1 Upstream Port Implementation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Downstream Port 1 Implementation
      3. 7.2.3 Downstream Port 2 Implementation
      4. 7.2.4 VBUS Power Switch Implementation
      5. 7.2.5 Clock, Reset, and Miscellaneous
      6. 7.2.6 Power Implementation
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply
    2. 8.2 Downstream Port Power
    3. 8.3 Ground
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Placement
      2. 9.1.2 Package Specific
      3. 9.1.3 Differential Pairs
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.1.3 Differential Pairs

This section describes the layout recommendations for all of the TUSB4020BI-Q1 differential pairs: USB_DP_XX, USB_DM_XX.

  • Must be designed with a differential impedance of 90 Ω ±10%.
  • To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Separate each pair by at least 5× the signal trace width. Separating with ground as depicted in the layout example also helps minimize crosstalk.
  • Route all differential pairs on the same layer adjacent to a solid ground plane.
  • Do not route differential pairs over any plane split.
  • Adding test points causes impedance discontinuity, and therefore, negatively impacts signal performance. If test points are used, place the test points in series and symmetrically. The test points must not be placed in a manner that causes stub on the differential pair.
  • Avoid 90° turns in trace. Keep the use of bends in differential traces to a minimum. When bends are used, make sure the number of left and right bends are as equal as possible and that the angle of the bend is ≥135°. Take this action to minimize any length mismatch caused by the bends, and therefore, minimize the impact bends have on EMI.
  • Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace length for USB 2.0 differential-pair signals. Longer trace lengths require very careful routing to assure proper signal integrity.
  • Match the etch lengths of the differential pair traces (that is DP and DM). Make sure the USB 2.0 differential pairs do not exceed 50mil relative trace length difference.
  • Minimize the use of vias in the differential-pair paths as much as possible. If this is not practical, ensure that the same via type and placement are used for both signals in a pair. Place any vias used as close as possible to the TUSB4020BI-Q1 device.
  • Do not place power fuses across the differential-pair traces.