JAJSF91B April   2018  – March 2020 TLV62568A , TLV62569A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      sp sp sp代表的なアプリケーションの回路図
      2.      sp sp入力電圧5V時の効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 100% Duty Cycle Low Dropout Operation
      2. 7.3.2 Soft Startup
      3. 7.3.3 Switch Current Limit
      4. 7.3.4 Under Voltage Lockout
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enabling/Disabling the Device
      2. 7.4.2 Power Good
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

VIN = 5.0 V, TJ = 25 °C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
ISD Shutdown current into VIN pin EN = 0 V 0.01 2 µA
VUVLO Under voltage lock out VIN falling 2.3 2.45 V
under voltage lock out hysteresis 100 mV
TJSD Thermal shutdown TJ rising 150 °C
TJ falling 130
LOGIC INTERFACE
VIH High-level input voltage at EN pin 2.5 ≤ VIN ≤ 5.5 1.2 V
VIL Low-level input voltage at EN pin 2.5 ≤ VIN ≤ 5.5 0.4 V
tSS Soft startup time From EN high to 95% of VOUT nominal 0.9 ms
VPG Power good threshold VFB rising, referenced to VFB nominal 95%
VFB falling, referenced to VFB nominal 90%
VPG,OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5 V 100 nA
tPG,DLY Power good delay time VFB falling 40 µs
OUTPUT
VFB Feedback regulation voltage 0.588 0.6 0.612 V
IFB Input leakage current into FB pin VFB = 0.6 V 10 nA
RDS(on) High-side FET on resistance 100 mΩ
Low-side FET on resistance 60
ILIM High-side FET current limit TLV62569A, TLV62569AP 3 A
TLV62568A, TLV62568AP 2
fSW Switching frequency 1.5 MHz