9.5.3 I²C Control Behavior

Follow this procedure to write to the SNx5DP159 device I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP159 device 7-bit address and a zero-value W/R bit to indicate a write cycle.
2. The SNx5DP159 device acknowledges the address cycle by combination of A0 and A1.
3. The master presents the subaddress (I²C register within SNx5DP159 device) to be written, consisting of one byte of data, MSB-first.
4. The SNx5DP159 device acknowledges the subaddress cycle.
5. The master presents the first byte of data to be written to the I²C register.
6. The SNx5DP159 device acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SNx5DP159 .
8. The master terminates the write operation by generating a stop condition (P).

Follow this procedure to read the SNx5DP159 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP159 7-bit address and a zero-value W/R bit to indicate a write cycle.
2. The SNx5DP159 device acknowledges the address cycle by combination of A0 and A1.
3. The master presents the subaddress (I2C register within SNx5DP159 device) to be read, consisting of one byte of data, MSB-first.
4. The SNx5DP159 device acknowledges the subaddress cycle.
5. The master initiates a read operation by generating a start condition (S), followed by the SNx5DP159 7-bit address and a one-value W/R bit to indicate a read cycle.
6. The SNx5DP159 device acknowledges the address cycle.
7. The SSNx5DP159 device transmit the contents of the memory registers MSB-first starting at the written subaddress.
8. The SNx5DP159 device will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
9. If an ACK is received, the SNx5DP159 device transmits the next byte of data.
10. The master terminates the read operation by generating a stop condition (P).

NOTE

Upon reset, the SNx5DP159 sub-address will always be set to 0x00. When no subaddress is included in a read operation, the SNx5DP159 subaddress increments from previous acknowledged read or write data byte. If it is required to read from a subaddress that is different from the SNx5DP159 internal subaddress, a write operation with only a subaddress specified is needed before performing the read operation.

Refer to Table 6 for the SNx5DP159 device local I²C register descriptions. Reads from reserved fields return 0s and writes are ignored.