JAJSF94F July   2015  – May 2018 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP159マザーボード・アプリケーションの構造
      2.      DP159ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.5.4.2.3 HDMI Control

Table 8. HDMI Control

ADDRESS BIT DEFAULT DESCRIPTION ACCESS
0Bh 7:6 2’b00 SLEW_CTL. Slew rate control.2’00 is fastest and 2’b11 is slowest
Writes ignored when I2C_EN/PIN = 0 		RWU
5 1’b0 HDMI_SEL: Contro; Writes ignored when I2C_EN/PIN = 0l
0 – HDMI (default)
1 – DVI		 RWU
4:3 2’b00 TX_TERM_CTL: Controls termination for HDMI TX
00 – No termination
01 – 150 to 300-Ω
10 – Reserved
11 – 75 to 150-Ω
Note: Reflects the value of the TX_TERM_CTL pin; Writes ignored when I2C_EN/PIN = 0 		RWU
2 1’b0 Reserved R
1 1’b0 TMDS_CLOCK_RATIO_STATUS: This field is updated from snoop of I2C write to slave address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/SCL_SRC interface. When bit 1 of address 0xA8 offset 0x20 is written to a 1’b1, then this field will be set to a 1’b1. When bit 1 of address 0xA8 offset 0x20 is written to a 1’b0, then this field will be set to a 1’b0. This field is reset to the default value whenever HPD_SNK is de-asserted for greater than 2 ms.
0 – TMDS clock is 1/10 of TMDS bit period (default)
1 – TMDS clock is 1/40 of TMDS bit period 		RWU
0 1’b0 DDC_TRAIN_SET: This field indicates the DDC training block function status. If disabled, the device can only work at the HDMI1.4b[2] or DVI mode
0 – DDC training enable (default)
1 – DDC training disable
Note: To force TMDS_CLOCK_RATIO_STATUS to 1, this register bit must be set to 1 which will force the 1/40 mode for HDMI2.0. 		RW
0Ch 7:5 3’b000 VSWING_DATA: Data output swing control
000 – Vsadj set
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
111 – Decrease by 7%		 RW
4:2 3’b000 VSWING_CLK: Clock Output Swing Control
000 – Vsadj set
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
111 – Decrease by 7%
Note: Default is set by DR, which means standard based swing values but this allows for the swing to be overridden by selecting one of these values		 RW
1:0 2’b00 HDMI_TWPST1. HDMI de-emphasis FIR post-cursor-1 signed tap weight.
00 – No de-emphasis
01 – 2-dB de-emphasis
10 – Reserved
11 – Reserved		 RWU